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This article reports that the enhanced forward gate bias time-dependent dielectric breakdown (TDDB) reliability and interface quality are achieved in 5-nm ferroelectric Hf0.5Zr0.5O2 (HZO) technologies by using the NH3 plasma interfacial layer (IL) treatment and microwave annealing (MWA). An orthorhombic crystalline phase is observed in the annealed HZO film with NH3 plasma IL treatment and MWA, and NH3 plasma IL treatment can suppress Hf/Zr interdiffusion. Metal-oxide-semiconductor capacitors (MOSCAPs) subjected to NH3 plasma IL treatment and 2100-W MWA also have a higher extrapolated operating voltage for a ten-year lifetime at 0.01% failure and lower interface state density (Dit) compared to the devices subjected to only rapid thermal annealing (RTA) at 600 °C. Therefore, NH3 plasma treatment and MWA are effective for improving the TDDB reliability and interface quality of the ultrathin ferroelectric HZO. [ABSTRACT FROM AUTHOR]

Effects of oxidation and nitric oxide (NO) post-oxidation annealing (POA) processes on the gate oxide integrity on 4H-SiC are investigated. Interface state density, flatband voltage, electron tunneling barrier height, breakdown field, and time-dependent dielectric breakdown are extracted. With the same NO POA condition, more nitrogen atoms are incorporated into wet oxide than dry oxide. The interface state density can be passivated effectively. At the same time, the electron tunneling barrier height at the SiO 2 /SiC interface approaches the ideal barrier height while positive charges would be introduced in oxide. NO annealing does not affect the breakdown field significantly. Regarding the time-dependent dielectric breakdown (TDDB) reliability, with increasing NO annealing time, the 10-year-projected intrinsic breakdown field decreases. It is concluded that NO annealing is effective in reducing the density of interface traps and hole traps originated from carboxyl defects, but excessive amount of nitrogen will turn into hole traps and thus deteriorates TDDB performance. • With the same NO POA condition, more nitrogen atoms are incorporated into wet oxide than dry oxide. • With nitrogen incorporation, the interface state density can be passivated effectively. • Wet oxidation results in slightly higher breakdown field while NO POA slightly reduces the breakdown field • With increasing NO annealing time, the 10-year-projected intrinsic breakdown field decreases for both wet and dry oxidation samples. • Excessive amount of nitrogen will turn into hole traps and thus deteriorates TDDB reliability of gate oxide on 4H-SiC. [ABSTRACT FROM AUTHOR]

The aim of achieving E-mode operations has led to the proposal of novel hybrid ferroelectric charge trap gate stack schemes. These schemes involve utilizing a combination of the charge trapping layer (CTL) and the ferroelectric laminated layer to positively shift the threshold voltage to a normally-off margin after initializing the gate pulse, thus achieving the Enhancement-mode (E-mode) characteristic. This study focuses on the forward gate bias time-dependent dielectric breakdown (TDDB) gate reliability in the E-Mode GaN MIS-HEMTs using ferroelectric charge trap gate stack (FEG-HEMT) with and without recess and investigates the impact of temperature on TDDB. The gate voltages required for operation with a 1 % failure rate over a 10-year period are 12.95 V and 10.22 V at 25 °C and 150 °C for both samples, respectively. Also, the examination of the stability of the recessed process by calculating the activation energies (0.7 eV) of both samples are demonstrated. The article also investigates the relationship between long-term reliability and short-term initialization by examining the transition point of the time-dependent failure curve. • The aim of achieving E -mode operations has led to the proposal of novel hybrid ferroelectric charge trap gate stack schemes. • This study focuses on the forward gate bias time-dependent dielectric breakdown (TDDB) gate reliability in the E-Mode GaN MIS-HEMTs using ferroelectric charge trap gate stack (FEG-HEMT) • The gate voltages required for operation with a 1% failure rate over a 10-year period are 12.95V and 10.22V at 25°C and 150°C for both samples, respectively. • Also, the examination of the stability of the recessed process by calculating the activation energies (0.7eV) of both samples are demonstrated. [ABSTRACT FROM AUTHOR]

In this work, the time-dependent dielectric breakdown (TDDB) analysis is performed to understand the gate oxide reliability in SiC MOSFETs with two different structures, i.e., planar and trench gate structures. We have discovered different gate leakage current behaviors between the SiC MOSFETs with planar gate (Sample A) and trench gate (Sample B) during the forward gate bias stress. Notably, the slight increase of the gate current during the stress and the negative activation energy (E a = −0.07 eV) observed in Sample A suggest that the hole generation caused by the impact ionization can be occurred during the forward gate TDDB tests. Furthermore, the SiC MOSFETs with trench gate structure (Sample B) exhibit the operation voltage of 55.7 V (exponential law) and 57.3 V (power law) for the 0.001 % failure of 30 years under 175 °C, indicating that SiC trench gate MOSFETs with enough thick gate dielectric (87.1 nm (bottom) and 77.9 nm (sidewall)) can have the promising forward gate TDDB stability. • The time-dependent dielectric breakdown (TDDB) analysis is performed to understand the gate oxide reliability in SiC MOSFETs • Different gate leakage current behaviors between the SiC MOSFETs with planar gate and trench gate • The negative activation energy observed in SiC planar MOSFETs suggests that the hole generation caused by the impact ionization • SiC trench gate MOSFETs with enough thick gate dielectric can have the promising forward gate TDDB stability. [ABSTRACT FROM AUTHOR]