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High quality sub-10 nm high-k dielectrics are deposited on top of MoS2 and evaluated using a dual-gate field effect transistor configuration. Comparison between top-gate HfO2 and an Al2O3/HfO2 bilayer shows significant improvement in device performance due to the insertion of the thin Al2O3 layer. The results show that the Al2O3 buffer layer improves the interface quality by effectively reducing the net fixed positive oxide charge at the top-gate MoS2/high-k dielectric interface. Dual-gate sweeping, where both the top-gate and the back-gate are swept simultaneously, provides significant insight into the role of these oxide charges and improves overall device performance. Dual-gate transistors encapsulated in an Al2O3 dielectric demonstrate a near-ideal subthreshold swing of ∼60 mV/dec and a high field effect mobility of 100 cm2/V·s. [ABSTRACT FROM AUTHOR]

A high quality Al2O3 layer is developed to achieve high performance in top-gate MoS2 transistors. Compared with top-gate MoS2 field effect transistors on a SiO2 layer, the intrinsic mobility and subthreshold slope were greatly improved in high-k backside layer devices. A forming gas anneal is found to enhance device performance due to a reduction in the charge trap density of the backside dielectric. The major improvements in device performance are ascribed to the forming gas anneal and the high-k dielectric screening effect of the backside Al2O3 layer. Top-gate devices built upon these stacks exhibit a near-ideal subthreshold slope of ~69 mV/dec and a high Y-Function extracted intrinsic carrier mobility (μo) of 145 cm2/V.s, indicating a positive influence on top-gate device performance even without any backside bias. [ABSTRACT FROM AUTHOR]

High quality HfO 2 and Al 2 O 3 substrates are fabricated in order to study their impact on top-gate MoS 2 transistors. Compared with top-gate MoS 2 FETs on a SiO 2 substrate, the field effect mobility decreased for devices on HfO 2 substrates but substantially increased for devices on Al 2 O 3 substrates, possibly due to substrate surface roughness. A forming gas anneal is found to enhance device performance due to a reduction in charge trap density of the high-k substrates. The major improvements in device performance are ascribed to the forming gas anneal. Top-gate devices built upon Al 2 O 3 substrates exhibit a near-ideal subthreshold swing (SS) of ~ 69 mV/dec and a ~ 10 × increase in field effect mobility, indicating a positive influence on top-gate device performance even without any backside bias. [ABSTRACT FROM AUTHOR]

Transition metal dichalcogenides (TMDs) have attracted intensive attention due to their atomic layer-by-layer structure and moderate energy bandgap. However, top-gated transistors were only reported in a limited number of research works, especially transistors with a high-k gate dielectric that are thinner than 10 nm because high-k dielectrics are difficult to deposit on the inert surface of the sulfide-based TMDs. In this work, the authors fabricated and characterized top-gated, few-layer MoS2 transistors with an 8 nm HfO2 gate dielectric. The authors show that the cleaning effect of ultrahigh vacuum annealing before high-k deposition results in significantly reduced gate leakage current of HfO2, and they show that N2 or a forming gas anneal after device fabrication affects the threshold voltage, drive current, dielectric leakage, and C-V frequency dependence. This work demonstrates how the fabrication process can affect the yield and the electrical characterization of top-gated TMD transistors, which in effect can help researchers further enhance the performance of their devices. [ABSTRACT FROM AUTHOR]