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A graphene wireless sensor concept is described. By utilizing thin gate dielectrics, the capacitance in a metal-insulator-graphene structure varies with charge concentration through the quantum capacitance effect. Simulations using realistic structural and transport parameters predict quality factors, Q, >60 at 1 GHz. When placed in series with an ideal inductor, a resonant frequency tuning ratio of 25% (54%) is predicted for sense charge densities ranging from 0.32 to 1.6 μC/cm2 at an equivalent oxide thickness of 2.0 nm (0.5 nm). The resonant frequency has a temperature sensitivity, df/dT, less than 0.025%/K for sense charge densities >0.32 μC/cm2. [ABSTRACT FROM AUTHOR]

Sulfur passivation of Ge(100) is achieved using aqueous ammonium sulfide (NH4)2S(aq). The passivation layer is largely preserved after atomic layer deposition of the high-κ dielectric material HfO2 when sufficiently low growth temperatures (e.g., 220 °C) are employed. Oxygen incorporation is moderate and results in an electrically passivating GeOS interface layer. The HfO2/GeOS/Ge gate stack exhibits lower fixed charge and interface state density than a more conventional HfO2/GeON/Ge gate stack fabricated via an ammonia gas treatment. [ABSTRACT FROM AUTHOR]

A facile, high‐resolution patterning process is introduced for fabrication of electrolyte‐gated transistors (EGTs) and circuits using a photo‐crosslinkable ion gel and stencil‐based screen printing. The photo‐crosslinkable gel is based on a triblock copolymer incorporating UV‐sensitive terminal azide functionality and a common ionic liquid. Using this material in conjunction with conventional photolithography and stenciling techniques, well‐defined 0.5–1 μm thick ion gel films are patterned on semiconductor channels as narrow as 10 μm. The resulting n‐type ZnO EGTs display high electron mobility (>2 cm2 Vs−1) and on/off current ratios (>105). Further, EGT‐based inverters exhibit static gains >23 at supply voltages below 3 V, and five‐stage EGT ring oscillator circuits display dynamic propagation delays of 50 μs per stage. In general, the screen printing and photo‐crosslinking strategy provides a clean room‐compatible method to fabricate EGT circuits with improved sensitivity (gain) and computational power (gain × oscillating frequency). Detailed device analysis indicates that significantly shorter delay times, of order 1 μs, can be obtained by improving the ion gel conductance. [ABSTRACT FROM AUTHOR]

Precise measurements of the mobility anisotropy along high-symmetry crystal axes in black phosphorus (BP) MOSFETs are reported. Locally back-gated BP MOSFETs with 13-nm HfO2 dielectric and channel length ranging from 0.3 to 0.7 $\mu \text{m}$ are fabricated. A single BP flake of a uniform thickness is exfoliated and etched along armchair (AC) and zigzag (ZZ) crystal axes, and the orientations are confirmed using optical and transmission electron microscopy analyses. The hole and electron mobilities along each direction are extracted using the transfer length method. The AC-to-ZZ hole mobility ratio is found to increase from 1.4 (1.5) to 2.0 (2.9) as the sheet concentration increased from $5.1\times 10^{\textsf {11}}$ to $1.9\times 10^{\textsf {12}}$ cm−2 at room temperature (77 K). The room-temperature electron mobility anisotropy is found to be similar to that for holes with an AC-to-ZZ mobility ratio increasing from 1.4 to 2.1 from $5.1\times 10^{\textsf {11}}$ to $1.9\times 10^{\textsf {12}}$ cm−2 though electrons showed only a very weak temperature dependence. A Boltzmann transport model is used to explain the concentration- and temperature-dependent mobility anisotropies which can be well described using a charge center scattering model. [ABSTRACT FROM AUTHOR]