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A new architecture is proposed which reduces the power consumption and capacitor area in successive approximation register (SAR) analogue-to-digital converters (ADCs). Two identical capacitor-splitting capacitor arrays are used in a two-step process for quantisation, and this significantly reduces the switching power and capacitor area. [ABSTRACT FROM AUTHOR]

A discrete-time ΔΣ analogue-to-digital converter utilising a multi-bit successive approximation register quantiser and a segmented digitalto-analogue converter (DAC) is proposed. By adding the delayed DAC output to the modulator input and removing it at the modulator output in the digital domain, the mismatch error is filtered. Thus, a first-order DAC mismatch error shaping is realised. This improves the DAC linearity without introducing an extra delay in the feedback path. Segmenting the DAC and processing the least significant bit and most significant bit segments separately, the dynamic range remains unaffected. [ABSTRACT FROM AUTHOR]

A novel double-sampling integrator is proposed, which is insensitive to path mismatch, and does not require bilinear integration. It allows the use of efficient design methods for ΔΣ ADCs. [ABSTRACT FROM AUTHOR]