Search

This paper presents an efficient architecture for two-dimensional (2-D) adaptive FIR filter architecture using the distributed arithmetic (DA) algorithm. DA-based filter architectures essentially require look-up tables (LUT). In the proposed filter architecture, RAM- or ROM-based LUT is replaced by adders- and logic gates-based structure that generates the LUT value corresponding to the input. Therefore, the MAC unit requires fewer logic gates and adders in DA-based realization. In addition, the memory sharing concept in architecture reduces the delay elements. Moreover, the complexity of the LUT hardware of higher-order filters is reduced by parallelly dividing the internal MAC block for the DA decomposition which offers a higher degree of modularity and parallelism in the proposed architecture. Further, 2-D delayed LMS algorithm is used for the updation of the filter coefficient weights. Furthermore, two-stage pipelining is used to reduce the critical path of the architecture and it also makes critical path delay independent of the order of the filter. ASIC synthesis results reveal the advantages of the proposed structure by reducing the area, power, ADP and EDP by 54%, 48.19%, 55% and 49%, respectively, as compared with the existing architecture for filter size 8 × 8. [ABSTRACT FROM AUTHOR]

This paper presents a generalized formulation of 2-D IIR filters using distributed arithmetic (DA) techniques. Based on the DA formulation, two efficient structures for 2-D IIR filters are proposed. Hardware-based look-up table (HLUT) is used in the internal blocks, so the proposed structures are reconfigurable. A novel approach of HLUT sharing, among the various internal blocks of structure, is used to reduce the requirement of adders and memory elements. For higher-order 2-D IIR filter, the complexity of HLUT is reduced by dividing the internal block of 2-D IIR filter into parallel and small block for DA decomposition. Such decomposition for higher-order 2-D IIR filters offers high degree of modularity, parallelism and regularity in building blocks, thereby achieving easier hardware and software implementation. In order to reduce combinational delay in the critical path, pipelining is used in the structures. Since proposed structures are multiplier-less and require lesser number of delays and adders, a significant improvement in chip area, power consumption and throughput can be obtained. Finally with the help of ASIC synthesis results, a comparative analysis is made and the results show that for the filter order 15, the proposed structures offer 69 and 59% reduction in ADP and 79 and 76% reduction in ADP than the earlier reported results for separable and non-separable structures, respectively. [ABSTRACT FROM AUTHOR]