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Herein, the carrier lifetime in ≈5 × 1016 cm−3 n‐doped InxGa1−xAs layers is studied by diode current–voltage analysis and by time‐resolved photoluminescence. Two sets of hetero‐epitaxial layers are grown on semi‐insulating InP or GaAs substrates. The first set corresponds with a constant In content p + n stack, while the second set has a fixed x = 0.53 for the n‐layer, while containing various extended defect densities by using a strain relaxed buffer with different x. This results in threading dislocation densities (TDDs) between ≈105 cm−2 and a few 109 cm−2. It is shown that the overall trend of the recombination lifetime versus TDD can be described by a first‐order model considering a finite recombination lifetime value inside a dislocation core of 1 nm. For the generation lifetime, a strong electric‐field enhancement factor is found. Also, the residual strain in the n‐layer has an impact. Overall, the safe limit for TDD depends on the type of application and on the operation conditions (reverse diode bias). [ABSTRACT FROM AUTHOR]

In this paper we review the details and results of the replacement fin process technique used to successfully demonstrate InGaAs based channel devices from FinFets to ultra scaled nanowires on 300 mm Si substrates. For FinFet devices a Mg p-type doping solution was developed to counteract the unintentional n-type doping of the InP buffer layer which resulted in high source-drain leakage. However, the performance of these devices is found to be limited by the Mg doping as the mobility is degraded. By switching to a GAA architecture the problem of source-leakage through the InP buffer is effectively eliminated and best devices with L G = 60 nm have a peak transconductance of 1030 μS/μm with a SS SAT of 125 mV/dec are achieved. A comparison of gate first to gate last processing highlights the importance of using a low thermal budget process to maintain the integrity of the InGaAs/high- k interface. Nanowires with a diameter of 6 nm were demonstrated to show quantization induced immunity to D it resulting in a SS SAT as low as 66 mV/dec for 85 nm L G devices. [ABSTRACT FROM AUTHOR]