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This article reveals the leakage mechanisms corresponding to the dominant leakage path of individual tail cells in $2\times $ nm technology double data rate (DDR)4 DRAM at operating temperature. For leakage path determination, activation energy (${E}_{a}$) was used as a tool through its extraction by retention time measurement. To get a wide distribution of ${E}_{a}$ , retention testing was performed at the target retention time (10, 15, 20, or 25 s); during this, the number of retentions failed cells were recorded with each temperature. In this experiment, 1.65 e−2% of the selected bank cells found retention failures. From the total retention failed cells, the selected commonly retention failed cells at the target retention times comprise 1.5 e−3% of the selected bank cells. From commonly retention failed cells, the distribution of ${E}_{a}$ is analyzed with the retention time at room temperature. This analysis reveals that subthreshold, junction, and gate-induced drain leakage (GIDL) leakage paths dominate in 3.48%, 93.89%, and 2.61% of the total retention failed cells, respectively, at room temperature. Using another experimental approach, retention testing performed at operating temperature on selected 0.07-ppm retention tail cells concludes that GIDL is the dominant leakage path in this device. Correlation between ${E}_{a}$ and retention time measured at operating temperature (40 °C, 60 °C, or 80 °C) explored the leakage mechanisms corresponding to ${E}_{a}$ of the extracted dominant leakage path (GIDL). These failure leakage mechanisms, dominating on certain values of operating temperature, are divulged as the root cause of failure at that temperature. [ABSTRACT FROM AUTHOR]

Dynamic random access memory (DRAM) bits can be erroneously flipped when the row near the error bits is repeatedly accessed with the activate and precharge commands in a process called row hammering. The trap at an Si–SiO2 interface has been previously reported as the leading cause of such errors. The number of row hammering required for flipping bits initially decreases and then saturates with the increases in the row precharge time ($t_{\mathrm {RP}}$). The DRAM timing parameter is the time interval between an activate command and a precharge command. This study uses the saturation $t_{\mathrm {RP}}$ to estimate the electron emission time of the trap associated with a DRAM bit error. During $t_{\mathrm {RP}}$ time, the traps at the Si–SiO2 interface emit the trapped electrons. There are more chances of emission as $t_{\mathrm {RP}}$ increases, and less row hammering is needed. The emission time of a trapped electron is experimentally measured herein using commercial DDR4 components. The components are irradiated with gamma rays to induce the interface traps. The trap characteristics are then extracted without requiring an additional measurement setup with a device-level preparation. The trap energies with respect to the mid-band at the Si–SiO2 interface are 0.118–0.280 eV. The trap energies are distributed within approximately 5.6 kT energies at room temperature. [ABSTRACT FROM AUTHOR]

This work shares the observations of stuck bits by proton beam in DDR3 components in 3x-nm technologies. The DDR3 SDRAMs from four major DRAM manufacturers were tested with a 45-MeV proton beam at an operating frequency of 800 MHz. The beam exposure resulted in single bit upset (SBU) and multiple bit upsets (MBUs), as well as single and multiple stuck bits in a word due to micro-dose and displacement damage effects. The number of stuck bits reduced as the refresh interval duration was decreased. Moreover, for the tested samples, the stuck bits were recovered completely and could be run in the normal operation mode after annealing at 150^\circC. The occurrence of multiple stuck bits in a word was likely due to damages to the control logic and those stuck bits were recovered as well after annealing at 150^\circC. [ABSTRACT FROM PUBLISHER]

This paper shares the effects of row hammer fault through high-energy proton radiation. The significance of row hammer fault is highlighted in terms of two different technologies in DDR4 SDRAM. Row hammer stress prevents nearby storage cells from maintaining storage data within the retention time of 64-ms. The stress is worsened by the radiation damage in silicon due to the high-energy particles. Proton-based radiation damage tests were performed with DDR4 SDRAM components from two different technologies. Experiment results showed that after proton irradiation, the number of bit errors caused by the row hammering test increased about 41% and 66% in technologies 2x-nm and 2y-nm, respectively. With 2y-nm technology, bit errors started to appear from 5 K Number of Hammering (N HMR )—the equivalent of 500-μs retention time. For 2y-nm components, more than 90% of failed words had multiple failed cells, which could not be corrected by Single Error Correction and Double Error Detection (SEC-DED) codes. [ABSTRACT FROM AUTHOR]