Search

Fault current-limiting dynamic voltage restorers (FCL-DVRs), also named as dual-functional DVRs, involving both the FCL and the voltage compensation (VC) function, have attracted more attention. However, in case of the FCL-DVR operating in VC mode, either the high capacity of storage system in the dc-link or the oversizing of power converter is needed, and in case of the FCL-DVR operating in FCL mode both the high dc-link voltage and the oversizing of power converter are needed. Thus, in order to overcome these drawbacks, an improved FCL-DVR, which consists of an LC filter coupled with series coupling capacitor (LCC) at the ac side, is proposed in this article. The improved FCL-DVR using energy-optimized control strategy can not only perform the dual functions well, but also achieve the capacity optimization of FCL-DVR key components. The operating principle and performance of the proposed FCL-DVR under FCL and VC mode are elaborated, respectively. The optimal design of LCC and selection of FCL branch are studied in detail to ensure high stability and reliability for the proposed FCL-DVR operating in both modes. The simulation and experimental results clearly validate the effectiveness of the proposed topology and method. [ABSTRACT FROM AUTHOR]

This paper proposes a dual-function dynamic voltage restorer (DFDVR) with fault current-limiting capability. The new topology can operate under different modes: the short-circuit fault current-limiting mode and the compensation mode for voltage fluctuation. Different functions of the DFDVR are achieved by controlling a brake chopper circuit and antiparallel thyristors. During fault conditions, the antiparallel thyristors are deactivated to protect the dc-side capacitor, and the duration of the on- and off-periods of the semiconductor switch in the brake chopper circuit is controlled to adjust fault current amplitudes. During voltage sags, the antiparallel thyristors are activated, and the brake chopper circuit is turned off by controlling the gate turn-off thyristor in the brake chopper circuit, thus making the DFDVR similar to a conventional DVR. The control scheme and optimal parameter selection of the DFDVR are provided. The design methodology of the DFDVR was verified through simulations performed using the PSCAD/EMTDC software. The experimental results prove the capability and effectiveness of the DFDVR topology. [ABSTRACT FROM AUTHOR]

This paper proposes a novel bridge-type solid-state fault current limiter based on dynamic voltage restorer (BFCL-DVR). The new topology uses a DC-link in the back-to-back converter of DVR. The proposed BFCL-DVR is equivalent to the conventional DVR during normal operation mode. At fault inception, the controller deactivates the series converter IGBTs in faulty phase and activates the DC-link semiconductor switches, thus establishing an equivalent bridge-type current limiter to restrict the fault current. The magnitude of the fault current is adjustable by controlling the frequency and duty ratio of the semiconductor switch that is in parallel with the discharging resistance. Moreover, the device is able to quickly recover from the current limiting mode to the normal operation mode. In this study, the operation sequence, optimal value of discharging resistance, duty cycle, and frequency of semiconductor switches are obtained. The design methodology of the proposed BFCL-DVR is fully verified using PSCAD/EMTDC software. Experimental results validate the proposed topology and theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper presents a new multilevel cascaded-type dynamic voltage restorer (MCDVR) with a fault current-limiting function. This topology can operate in two operational modes: 1) a compensation mode for voltage fluctuations and unbalances and 2) short-circuit current-limiting mode. The current-limiting function of the MCDVR is performed by activating antiparallel thyristors during the short-circuit fault, and deactivating them during normal operation. The mathematical model of the MCDVR system is also established in this paper. The control scheme design and optimal parameter selection are outlined based on the detailed theoretical analysis of the converter. The transient states of the MCDVR in the compensation mode and current-limiting mode are also analyzed. Simulation results based on the PSCAD/EMTDC software, and experimental results on a laboratory setup help to validate the proposed topology and the theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper proposes a new fault current limiting dynamic voltage restorer (FCL-DVR) concept. The new topology uses a crowbar bidirectional thyristor switch across the output terminals of a conventional back-to-back DVR. In the event of a load short, the DVR controller will deactivate the faulty phase of the DVR and activate its crowbar thyristor to insert the DVR filter reactor into the grid to limit the fault current. A fault condition is detected by sensing the load current and its rate of change. The FCL-DVR will operate with different protection strategies under different fault conditions. Design of the FCL-DVR involves selecting important parameters, such as DVR power rating, dc link voltage of the DVR, output filter reactors and capacitors, and grid-tied transformers is proposed. The design methodology of the proposed FCL-DVR is fully discussed based on power systems computer aided design (PSCAD)/electromagnetic transients including dc (EMTDC) simulation. A scaled-down experimental verification is also carried out. Both modeling and experimental results confirm the effectiveness of the new FCL-DVR concept for performing both voltage compensation and fault current limiting functions. [ABSTRACT FROM PUBLISHER]