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Highlights: [•] Wet oxidation at 950°C followed by NO anneal at 1175°C reduces the interface trap density to 4–6×1011 cm−2 eV−1. [•] The positive flat band voltage shift caused by low temperature wet oxidation can be suppressed by the following NO anneal. [•] The oxide breakdown fields for Al- and N-implanted C-face 4H-SiC samples are about 1.5 and 5MVcm−1, respectively. [•] The oxide breakdown field of dry oxidation at 950°C is the same as that of wet oxidation at 950°C. [ABSTRACT FROM AUTHOR]

Abstract: The goal of this research is to investigate the correlation of reverse characteristics of Schottky barrier diodes (SBDs) and surface morphological defects on 4° (off-axis) carbon (C) face, 4° and 8° silicon (Si) face 4H-SiC. Different dimensions of SBDs with boron-implanted edge terminations are fabricated on 4° C-face, 4° and 8° Si-face 4H-SiC samples. The ideality factor for these three samples is about 1.1. Average breakdown voltages of 4° Si-face 4H-SiC SBDs are higher than the other two samples, particularly for large size SBDs. Breakdown voltages of 1500 and 2000μm 4° Si-face SBDs can reach over 1000V. This value is about two times higher than the other two samples, though the root-mean-square (RMS) roughness of 4° Si-face samples obtained from atomic force microscopy (AFM) is 3.5nm. The yield of 1500 and 2000μm 4° Si-face 4H-SiC SBDs with a breakdown voltage over 1000V is more than 50%, much higher than the other two samples. [Copyright &y& Elsevier]

This work demonstrates a trench isolated lateral double-implanted MOSFET (LDMOS) on Si-face in 4H-silicon carbide (SiC). A device $\vphantom {_{\int _{}}}$ where ${L}_{\textit {ch}} = 0.8\,\,\mu \text{m}$ and ${L}_{d} = 12\,\,\mu \text{m}$ shows an ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 22.9 $\text{m}\Omega $ cm2 at a ${V}_{\text {GS}}$ of 20 V and a breakdown voltage (BV) of 1100 V, corresponding to a high BV2/ ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 55.5 MW/cm2. Devices that have different ${L}_{\text {ch}}$ , ${L}_{\text {JFET}}$ , ${L}_{d}$ , and P-top dose values are measured in order to investigate the effects of geometry on the static performance. Operations at 150 °C are measured to evaluate the temperature performance. Gate charge waveforms are also measured in order to include the switching performance in the evaluation. The ${R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{G}$ and ${R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{\text {GD}}$ values are calculated as 17.7 and $9.0~\Omega $ nC, respectively, which are promising for power-integrated circuit applications. [ABSTRACT FROM AUTHOR]

In this paper, a comparison of different techniques for SiC high-voltage devices is performed using numerical simulations. In particular, the method of counter doping (CD) introduced in the junction termination extension (JTE) region to create a multizone termination effect is investigated. Simulation shows that compared with the other edge termination techniques, CD-JTE greatly reduces the sensitivity of breakdown voltage (BV) to JTE doses and surface charges. The multizone CD-JTE with outer rings shows that for a 30- \mu m thick epi-layer, 90% of the theoretical BV is achievable with a wide tolerance of 11\,\times \,10^{\mathrm {12}} /cm ^{2} to the JTE dose and 85% of the theoretical BV with an increased tolerance of 6.19\times 10^\mathrm 12 /cm ^2 to the positive surface charges, both superior to other JTE structures investigated in this paper. [ABSTRACT FROM AUTHOR]