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A high-speed and high-accuracy continuous-time common-mode feedback block (CMFB) is presented. To satisfy speed and accuracy requirements, some modifications have been applied on differential difference amplifier (DDA) CMFB circuit. The proposed method is applied to a folded cascode op-amp with power supply of 3.3 V. In order to verify the proposed circuit, simulations are done in 0.35 μm standard CMOS technology. In the worst condition when the output common-mode (CM) voltage is initialized to VCC or GND, only 1.1 ns is required to set the output CM voltage on the desired level. Also in a wide range of input CM voltage variations, the deviation of the output CM voltage from reference voltage is less than 6 mV, so simulation results confirm the expected accuracy and speed while simultaneously the proposed CMFB circuit preserves other characteristics of DDA CMFB circuit such as unity gain frequency, 3-dB bandwidth, phase margin and linearity. [ABSTRACT FROM AUTHOR]

In this article, an analog fully programmable membership function generator (MFG) is presented. It is capable of generating Gaussian, Triangular and Trapezoidal shapes as well as S or Z shapes. For omitting noise disturbances, differential structures are utilized in input and output stages which are in voltage mode and current mode, respectively. In contrast with conventional MFGs which are controlled digitally or by mixed signal approaches, this structure is a fully programmable analog MFG. It is capable of modifying slope, position and height of output's current. The most distinguishing features of this MFG are its capability of generating ultra-high speed outputs reaching speeds as high as 200 MHz and consuming a very low amount of power. Due to the simple structure of this MFG, it consumes a small active area at the size of 20 μm × 30 μm. It is constructed of only 16 transistors. This MFG has been designed in 0.35 μm CMOS technology. The simulations have been done with Hspice using TSMC, BSIM3 (V3.1) model. [ABSTRACT FROM AUTHOR]

This paper proposes the method to implement a general form of membership functions for fuzzy systems in CMOS technology. These membership functions are a general form of triangular types and those functions which are used in linguistic hedge fuzzy logic, hence can offer better performance in almost all applications. The comparison between the proposed method and previously reported works shows better performance in all parameters. Designed circuits to implement these types of membership functions are simulated using HSPICE by level 49 parameters (BSIM3v3) in 0.35 μm standard CMOS technology. Current mode realization of the circuits leads to simple and intuitive configurations. The Rational Power Generator Module (RPGM) generates powers with the resolution of 0.03125 and using seven programming bits. The simulation results of RPGM demonstrate a RMS error of 1.42% and a maximum power consumption of 1.05 mW. [ABSTRACT FROM AUTHOR]

Abstract: A novel single-stage second-order structure for Gm-C filters is presented. It allows ample reduction in hardware and thus power consumption. Moreover, due to exploiting otherwise parasitic poles, the structure allows much higher bandwidth than in conventional designs, be achieved. To verify effectiveness of new concept, and based on the new approach to implement second-order stages, a third-order and a fifth-order continuous-time low-pass filters were implemented. The filters fabricated in a CMOS process, achieved more than 430MHz, bandwidth and less than THD for a 400m 100MHz input signal. All these accomplished with a factor of about four reduction in hardware and power. The bandwidth, output voltage swing, and dynamic range are far larger than those of any other CMOS low-pass filters thus far reported, which have bandwidth higher than 100MHz. [Copyright &y& Elsevier]

Abstract: In this paper a new CMOS current-mode four-quadrant analog multiplier and divider circuit based on squarer circuit is proposed. The dual translinear loop is the basic building block in realization scheme. Supply voltage is 3.3V. The major advantages of this multiplier are high speed, low power, high linearity and less dc offset error. The circuit is designed and simulated using HSPICE simulator by level 49 parameters (BSIM3v3) in standard CMOS technology. The simulation results of analog multiplier demonstrate a linearity error of 1.1%, a THD of 0.97% in 1MHz, a bandwidth of 41.8MHz and a maximum power consumption of 0.34mW. [Copyright &y& Elsevier]