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This paper reports the analyses of the inductive degeneration, noise filter, and optimum current density techniques for phase noise reduction in the CMOS Hartley oscillator circuit topology. The design of the circuit topology is carried out in 28 nm bulk CMOS technology in a range of common conditions adopted also for a previous study on the Colpitts topology, so complementing the previous study on Colpitts topology and allowing a direct comparison between the Hartley and Colpitts topologies. The theoretical analyses of the three techniques are carried out and verified by means of circuit simulations. The results obtained for the inductive degeneration and noise filter show the existence of an optimum inductance for minimum phase noise. Moreover, the results obtained for the optimum bias current density technique applied to a Hartley oscillator circuit topology incorporating either inductive degeneration or noise filter provide the demonstration of the existence of an optimum bias current density for minimum phase noise. Moreover, we will go beyond this important result, by investigating for the first time the relationship with the optimum current density for transistor minimum noise figure and other general results reported in the literature. Overall, the analyses show that the adoption of these techniques may lead to a potential phase noise reduction up to 16 dB at a 1 MHz frequency offset for an oscillation frequency of 10 GHz, with respect to the traditional Hartley topology. Lastly, we report a comparison under common conditions between Colpitts and Hartley topologies implementing the aforementioned techniques, which could, from a designer perspective, be useful to acquiring a few key insights about the circuit design opportunities and focus the design efforts toward specific directions for performance optimizations. Copyright © 2017 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

This paper presents a 67GHz LC oscillator exploiting a three-spiral transformer and implemented in 65nm bulk complementary metal-oxide-semiconductor technology by STMicroelectronics. The three-spiral transformer allows operating with a lower voltage supply, still obtaining good phase noise performance, and achieving a compact design. Measured performances when supplied with 1.2 V are: oscillation frequency of 67 GHz, phase noise ( PN) equal to −96 dBc/Hz at 1 MHz frequency offset from the carrier, power consumption ( PC) equal to 19.2 mW and figure of merit ( FOM) equal to −179.7 dB/Hz. Measured performances when supplied with 0.6 V are: oscillation frequency of 67 GHz; PN equal to −88.7 dBc/Hz at a 1 MHz frequency offset from the carrier; PC equal to 3.6 mW and FOM equal to −179.7 dB/Hz. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

Comparative Phase Noise analyses of common-source cross-coupled pair, Colpitts, Hartley and Armstrong differential oscillator circuit topologies, designed in 28 nm bulk CMOS technology in a set of common conditions for operating frequencies in the range from 1 GHz to 100 GHz, are carried out in order to identify their relative performance. The impulse sensitivity function (ISF) is used to carry out qualitative and quantitative analyses of the noise contributions exhibited by each circuit component in each topology, allowing an understanding of their impact on phase noise. The comparative analyses show the existence of five distinct frequency regions in which the four topologies rank unevenly in terms of best phase noise performance. Moreover, the results obtained from the ISF show the impact of flicker noise contribution as the major effect leading to phase noise degradation in nanoscale CMOS LC oscillators. [ABSTRACT FROM AUTHOR]