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In the first part of this paper, three-phase power factor correction (PFC) rectifier topologies with sinusoidal input currents and controlled output voltage are derived from known single-phase PFC rectifier systems and/or passive three-phase diode rectifiers. The systems are classified into hybrid and fully active pulsewidth modulation boost-type or buck-type rectifiers, and their functionality and basic control concepts are briefly described. This facilitates the understanding of the operating principle of three-phase PFC rectifiers starting from single-phase systems, and organizes and completes the knowledge base with a new hybrid three-phase buck-type PFC rectifier topology denominated as Swiss Rectifier. Finally, core topics of future research on three-phase PFC rectifier systems are discussed, such as the analysis of novel hybrid buck-type PFC rectifier topologies, the direct input current control of buck-type systems, and the multi-objective optimization of PFC rectifier systems. The second part of this paper is dedicated to a comparative evaluation of four rectifier systems offering a high potential for industrial applications based on simple and demonstrative performance metrics concerning the semiconductor stresses, the loading and volume of the main passive components, the differential mode and common mode electromagnetic interference noise level, and ultimately the achievable converter efficiency and power density. The results are substantiated with selected examples of hardware prototypes that are optimized for efficiency and/or power density. [ABSTRACT FROM AUTHOR]

This paper presents the design and implementation of a three-phase high power factor mains interface concept appropriate for many power electronic applications such as supplies for dc power distribution systems in telecommunication, electric vehicle battery charging, future more electric aircraft, variable-speed ac drives, and high power lighting systems. The circuit topology comprises a buck-type power factor correction rectifier circuit built by the combination of an active third-harmonic injection rectifier and a series-connected dc-dc buck-type converter. The characteristics of this rectifier topology, including the principles of operation, modulation strategy, suitable control structure, and dimensioning equations, are described in this paper. The feasibility of the presented converter for buck-type rectifier applications is demonstrated by means of a constructed hardware prototype. [ABSTRACT FROM AUTHOR]

Due to their basic physical properties, power MOSFETs exhibit an output capacitance Coss that is dependent on the drain-source voltage. This (nonlinear) parasitic capacitance has to be charged at turn-off of the MOSFET by the drain-source current in rectifier applications that yield input current distortions. A detailed analysis shows that the nonlinear behavior of this capacitance is even more pronounced for modern super junction MOSFET devices. Whereas Coss increases with increasing chip area, the on-state resistance of the MOSFET decreases accordingly. Hence, a tradeoff between efficiency and input current distortions exists. A detailed analysis of this effect considering different semiconductor technologies is given in this study and a Pareto curve in the η-THDI space is drawn that clearly highlights this relationship. It is further shown that the distortions can be reduced considerably by the application of a proper feedforward control signal counter- acting the nonlinear switching delay due to Coss. The theoretical considerations are verified by experimental results taken from 10-kW laboratory prototypes with the switching frequencies of 250 kHz and 1 MHz. [ABSTRACT FROM AUTHOR]

In telecom applications, the vision for a total power conversion efficiency from the mains to the output of point-of-load (PoL) converters of 95% demands optimization of every conversion step, i.e., the power factor correction (PFC) rectifier front-end should show an outstanding efficiency in the range of 99%. For recently discussed 400-V dc distribution bus voltages, a buck-type PFC rectifier is a logical solution. In this paper, an efficiency-optimized, 98.8% efficient, 5-kW three-phase buck-type PFC rectifier with 400-V output is presented. Methods for calculating losses of all components are described and are used to optimize the converter design for efficiency at full load. Special attention is paid to semiconductor losses, which are shown to be dominant, with the parasitic device capacitance losses being a significant component. The calculation of these parasitic capacitance losses is treated in detail, and the charge-balance approach used is verified. A prototype of the proposed rectifier is constructed which verifies the accuracy of the models used for loss calculation and optimization. [ABSTRACT FROM AUTHOR]