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A wireless 3D NoC architecture is described for building-block SiPs, in which the number of hardware components (or chips) in a package can be changed after chips have been fabricated. The architecture uses inductive-coupling links that can connect more than two examined dies without wire connections. Each chip has data transceivers for the uplink and downlink in order to communicate with its neighboring chips in the package. These chips form a vertical unidirectional ring network so as to fully exploit the flexibility of the wireless approach that enables us to add, remove, and swap the chips in the ring. To avoid protocol and structural deadlocks in the ring, we use bubble flow control, which does not rely on the conventional VC-based deadlock avoidance mechanism. In addition, we propose a bidirectional communication scheme to form a bidirectional ring network by using the inductive-coupling transceivers that can dynamically change the communication modes, such as TX, RX, and Idle modes. This paper illustrates the inductive-coupling transceiver circuits, which can carry high data transfer rates of up to 8 Gbps per channel, for the wireless 3D NoC. It also illustrates an implementation of a wireless 3D NoC that has on-chip routers and transceivers implemented with a 65 nm process in order to show the feasibility of our proposal. The vertical bubble flow control and conventional VC-based approach on the uni- and bidirectional ring networks are compared with the vertical broadcast bus in terms of throughput, hardware amount, and application performance using a full system multiprocessor simulator. The results show that the proposed bidirectional communication scheme efficiently improves application performance without adding any inductive-coupling transceivers. In addition, the proposed vertical bubble flow network outperforms the conventional VC-based approach by 7.9-12.5 percent with a 33.5 percent smaller router area for building-block SiPs connecting up to eight chips. [ABSTRACT FROM PUBLISHER]

An inductive power and data transmission link for a noncontact memory card interface is reported. Nested clover coils improve signal-to-interference ratio and enable simultaneous power and data transmission. This capability is then used in the design of a closed-loop feedback system for improving power transfer efficiency. Interference cancellation mechanism is analyzed with both 3-D EM simulations and a newly developed compact model of coupled inductors. Performance of the proposed solutions was confirmed experimentally using a scaled-down stacked-chip prototype fabricated in a 65-nm CMOS process. Maximum data transmission rate is 6 Gb/s and the total power transfer efficiency is 5.2%–10.2% over a load resistance range of 0.1–2 k\Omega. [ABSTRACT FROM AUTHOR]

This paper presents a low-power inductive-coupling link in 90-nm CMOS. Our newly proposed transmitter circuit uses a charge-recycling technique for power-aware 3-D system integration. The cross-type daisy chain enables charge recycling and achieves power reduction without sacrificing communication performance such as a high timing margin, low bit error rate and high bandwidth. There are two design issues in the cross-type daisy chain: pulse amplitude reduction and another is inter-channel skew. To compensate for these issues, an inductor design and a replica circuit are proposed and investigated. Test chips were designed and fabricated in 90-nm CMOS to verify the validity of the proposed transmitter. Measurements revealed that the proposed cross-type daisy chain transmitter achieved an energy efficiency of 65 fJ/bit without degrading the timing margin, data rate, or bit error rate. In order to investigate the compatibility of the transmitter with technology scaling, a simulation of each technology node was performed. The simulation results indicate that the energy dissipation can be potentially reduced to less than 10 fJ/bit in 22 nm CMOS with proposed cross-type daisy chain. [ABSTRACT FROM AUTHOR]

In this paper, we report the world's first ac-coupled clock distribution circuit for low-power and high-frequency clock distribution. By employing the proposed ac-coupled LC-based voltage-controlled oscillator (LC-VCO) and phase interpolators, the use of conventional current-mode-logic (CML) buffers with large power requirements can be prevented, and power consumption for clock distribution can be reduced. With the aim of verifying the effectiveness of the proposed circuit, test chips were designed and fabricated in 0.18-\mum mixed-signal CMOS technology. The measured results indicated a 14.007 GHz clock distribution to four points whose pitches are 450 \mum, with 6.9 mW of power. The phase noise was measured to be -79.06 dBc/Hz at a 100 kHz offset, -101.66 dBc/Hz at a 1 MHz offset, and -107.25 dBc/Hz at a 10 MHz offset, with a clock frequency of 12.96 GHz. Furthermore, a phase averaging technique for reducing phase deviation was proposed and theoretically investigated. [ABSTRACT FROM PUBLISHER]

Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip links for 3-D system integration is introduced for the first time. Misalignment between stacked chips reduces coupling coefficiency of on-chip inductors and increases transmitter power. We proposed a modeling which estimates the increase in transmitter power by considering misalignment as an additional communication distance. Proposed model was verified by electromagnetic simulations and by measurements using testchips fabricated in 65-nm CMOS technology. The results calculated by the proposed modeling match well with measurement results. Measurement results show that misalignment tolerance of inductive-coupling link is well high and can be ignored in common conditions. [ABSTRACT FROM AUTHOR]

A 2 Gb/s bi-directional inter-chip data transceiver is experimentally demonstrated for the first time in 180 nm CMOS technology. Two orthogonal differential inductor pairs are vertically overlapped to make a bi-directional channel. Using these channels, bi-directional communication system is established without any complex circuit techniques. The crosstalk interference problem in channel array is also considered. Differential inductors, due to their noise immunity can make shorter pitches possible in channel array. Compared with the data link with conventional inductor array, this proposed technique achieves 64% area reduction with the same speed. [ABSTRACT FROM AUTHOR]

Inductive coupling among stacked chips in a package enables 1 Gb/s/channel data communications. Array arrangement of the channel increases data bandwidth, while signal may be degraded by crosstalk. In this paper, crosstalk is measured and analyzed, and crosstalk countermeasures are discussed. Received signal waveforms through the inductive coupling are measured by embedded voltage detectors on a test chip. Interference-to-signal ratio (ISR) has good agreement between the measurements and calculations. It is found that crosstalk is reduced negligibly at a certain distance. If the channels are arranged at intervals of this distance, ISR is minimized. A technique based on time interleaving is also proposed to further reduce crosstalk. A 3 × 17 channel array is implemented with the crosstalk countermeasures. The channel pitch is taken down to 50 μm. Inter-chip communication with data rate of 1 Gb/s/channel and bit error rate (BER) lower than 10-9 is demonstrated. [ABSTRACT FROM AUTHOR]

A 1 Tb/s 3 W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1 GHz and data rate of 1 Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30 µm in a layout area of 1 mm². The total layout area including 16 clock transceivers is 2 mm² in 0.18 µm CMOS and the chip thickness is reduced to 10 µm. Bi-phase modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. Four-phase time division multiple access (TDMA) reduces crosstalk and the bit-error rate (BER) is lower than 10-13. [ABSTRACT FROM AUTHOR]

A wireless interface by inductive coupling achieves aggregated data rate of 195 Gb/s with power dissipation of 1.2 W among 4-stacked chips in a package where 195 transceivers with the data rate of 1 Gb/s/channel are arranged in 50-μm pitch in 0.25-μm CMOS technology. By thinning chip thickness to 10 μm, the interface communicates at distance of 15 μm at minimum and 43 μm at maximum. A low-power single-end transmitter achieves 55% power reduction for multiple connections. The transmit power is dynamically controlled in accordance with communication distance to reduce not only power dissipation but also crosstalk. [ABSTRACT FROM AUTHOR]