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This paper proposes a control for a single-phase grid-tied inverter operating in both continuous current mode (CCM) and discontinuous current mode (DCM) to minimize inductors without worsening a current total harmonic distortion (THD). In a conventional CCM/DCM control, an inductance is required in a DCM nonlinearity compensation; consequently, the control becomes inductance-dependent. In the proposed control, a duty ratio at a previous calculation period is utilized to compensate for the DCM nonlinearity and detect current modes independently from the inductance. A 4-kW 100-kHz prototype of the inverter with two designs of the inductor is realized to confirm the effectiveness of the proposed control. When the inductor impedance, which is normalized by an inverter impedance, is reduced from 1.8% to 0.5%, volume and material cost of the inductor are reduced by 51% and 62%, respectively, whereas the loss at a light load of 0.1 p.u. is reduced by 35%. However, due to this inductor minimization, the current THD at a rated load increases from 2.3% to 8.7% with the conventional control, violating the grid current harmonic constraint regulated by standard IEEE-1547. The proposed CCM/DCM control reduces the current THD from 8.7% to 2.1%, enabling the inductor minimization and satisfies the grid standard. [ABSTRACT FROM AUTHOR]

Abstract: A novel circuit topology for a single‐phase inverter with a power decoupling capability operated in discontinuous current mode (DCM) is proposed in this paper. An inverter connected to a single‐phase grid requires a power decoupling capability to compensate for a power ripple with twice the grid frequency. Bulky capacitors are used as DC‐link capacitors in conventional systems. In contrast, the proposed circuit topology can use ceramic capacitors instead of electrolytic capacitors by reducing the required capacitance based on the active buffer concept. Moreover, this active buffer requires no additional inductor because it uses DCM for the power decoupling capability. In this paper, a control method for the active buffer circuit operated in DCM is introduced. An experimental verification of a 1‐kW prototype shows that the proposed circuit reduces the input current ripple at twice the grid frequency by 96.8%, with a maximum efficiency of 95.2%. In addition, the Pareto optimization of power density and efficiency is used to clarify the maximum power density points. It is found that the maximum power density of the proposed circuit is 1.6 times higher than that of a conventional boost‐type active buffer. [ABSTRACT FROM AUTHOR]

This paper proposes a square-wave control strategy for a single-phase power factor correction with a new boost-up converter which uses the leakage inductance of a motor instead of a boost-up reactor. Since the power supply is connected to the neutral point of the motor, the current distortion in the power supply occurs when the inverter outputs square waveforms. First, this paper describes the characteristic of the proposed circuit and the problems in the square-wave operation. Next, a current control method for the square waveform is proposed to suppress the current distortion. Finally, the validity of the proposed converter and its control strategy are demonstrated by experimental results. [ABSTRACT FROM PUBLISHER]

The proposed inverter combines two methods which can significantly decrease the on-state and switching losses. The first method, using a current transformer and a single transistor, makes possible the reduction of the on-state loss to less than one-third of the usual Darlington transistor. The second method, using an auxiliary commutation IGBT in parallel with the transistor, makes possible zero-voltage switching, resulting in no switching loss. To realize higher inverter efficiency, a snubber and its loss recovery circuit are employed. Three-phase inverters were fabricated experimentally to evaluate our idea. Device volume and weight can be decreased to one-third those of a conventional three-phase inverter, and an efficiency of 98.0% from 5 kW to 20 kW is obtained at a switching frequency of 16 kHz. © 1997 Scripta Technica, Inc. Electr Eng Jpn, 120(1): 62–69, 1997 [ABSTRACT FROM AUTHOR]

This paper proposes a zero-voltage ride-through (ZVRT) method and an LCL filter design method to meet the fault ride-through (FRT) requirements for a single-phase grid-connected inverter with a minimized LCL filter. A high inverter output current overshoot occurs at a grid voltage sag and a grid voltage recovery, when a low-inductance LCL filter design is employed in order to minimize the filter volume. In order to suppress the current overshoot, a high-speed gate-block operation and the design method of the minimized LCL filter are proposed. In particular, the filter design considers the delay time in the gate-block operation in order to clarify the reduction limitation of the inductance in the LCL filter. As a result, the maximum inverter output current overshoot is suppressed to 146% by the high-speed gate-block operation and the designed LCL filter, where the impedances of an interconnected inductor and a filter inductor are 1.0% and 0.78% of the inverter normalized impedance, respectively. Therefore, it is possible to meet the FRT requirements with the proposed ZVRT method even with the minimized LCL filter. [ABSTRACT FROM AUTHOR]

SUMMARY This paper proposes a configuration of a single-phase voltage source inverter that features power decoupling capability. Generally, the converter connected to a single-phase grid employs bulky dc link capacitors such as electrolytic capacitors in order to decouple the power ripple with twice the frequency of the power supply. The power ripple in the proposed circuit is compensated by an active buffer with small capacitors. In this paper, the fundamental operations of the proposed converter are confirmed by experimental results. From the experimental results, the output current total harmonic distortion (THD) is 3.51%, the ratio of the input current is 14.3%, and the output power factor is over 99%. In addition, the volume of the proposed circuit is reduced by 61% when the carrier frequency is 64 kHz compared to that with a carrier frequency of 16 kHz. Finally, from an evaluation of the power density using Pareto front curves, the proposed circuit achieves high power density in comparison with the conventional circuit. [ABSTRACT FROM AUTHOR]

In the present, a power decoupling method without additional component is proposed for a dc to single-phase ac converter, which consists of a flying capacitor dc/dc converter (FCC) and the voltage source inverter (VSI). In particular, a small flying capacitor in the FCC is used for both a boost operation and a double-line-frequency power ripple reduction. Thus, the dc-link capacitor value can be minimized in order to avoid the use of a large electrolytic capacitor. In addition, component design, of, e.g., the boost inductor and the flying capacitor, is clarified when the proposed control is applied. Experiments were carried out using a 1.5-kW prototype in order to verify the validity of the proposed control. The experimental results revealed that the use of the proposed control reduced the dc-link voltage ripple by 74.5%, and the total harmonic distortion (THD) of the inverter output current was less than 5%. Moreover, a maximum system efficiency of 95.4% was achieved at a load of 1.1 kW. Finally, the high power density design is evaluated by the Pareto front optimization. The power densities of three power decoupling topologies, such as a boost topology, a buck topology, and the proposed topology are compared. As a result, the proposed topology achieves the highest power density (5.3 kW/dm3) among the topologies considered herein. [ABSTRACT FROM AUTHOR]