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The power losses, current and voltage stresses in semiconductor devices in voltage source transformerless multilevel inverters (VSTMLIs) topologies are unequal, depending on the switching states, the duty ratio, the levels of output voltage, the load power factor and the depth of modulation index. Non-uniform power loss profiles mean both unequal junction temperature and power rating in semiconductors. In this study, a comparison of power losses, current and voltage stresses in semiconductors of VSTMLIs is performed. Initially, the structural characteristics and operating principles of dominant VSTMLIs with sinusoidal pulse width modulation are analysed. Then, modifications of existing VSTMLIs and simplified multilevel topologies are proposed, which achieve a further reduction in switch count and power losses in semiconductors. The proposed modified circuitries are suitable for converting existing four-level VSTMLI topologies into five-level ones. This conversion is desirable, when a zero output voltage level under no-load conditions or low modulation indices should be obtained. Power losses in semiconductors are calculated analytically and then confirmed by simulation. A comparative presentation of profiles of power losses, current and voltage stresses in semiconductors of the examined VSTMLIs is analytically carried out. The obtained results are valuable for sizing and selecting the semiconductors in VSTMLIs. [ABSTRACT FROM AUTHOR]

In this paper, a novel four-level inverter will be presented and analyzed. The proposed inverter topology, which is composed of a conventional two-level and a three-level neutral-point clamped (NPC) inverter, is suitable for high-voltage and high-power applications. The proposed inverter, when it is compared with the conventional four-level NPC pulsewidth modulation inverter, exhibits the following advantages: a) ability of changing the power losses distribution profile among the devices by selecting a suitable switching strategy; b) reduction of total inverter power semiconductor device losses; c) ability of bidirectional operation for all power semiconductor switches; and d) easy implementation using existing power semiconductor modules. The effect of conduction and switching losses profiles of the proposed inverter for different switching strategies is examined under different loads, power factors, and modulation indices. The dc-link capacitors voltages are effectively balanced via a proposed self-voltage balancing topology, without the need of isolated dc voltage sources or additional voltage stabilizing circuits. Finally, the theoretical results are confirmed by simulation and experimental results. [ABSTRACT FROM AUTHOR]

This paper presents a methodology for a convenient modification of induction motor equivalent circuit parameters, taking into consideration switching frequency Iron losses in case of inverter supply. The method is based on the determination of harmonic iron losses in laminated, iron cores under nonsinusoidal excitation by using a particular three-dimensional (3-D) finite-element model adopting a reduced scalar potential formulation. Eddy currents in iron laminations are considered by means of convenient surface current densities. Experimental verification is performed in case of a 20-kW experimental setup. [ABSTRACT FROM AUTHOR]