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A novel transient voltage suppressor (TVS) that features ultralow capacitance is proposed. This structure is able to reduce the input capacitance by 21.1%, and is designed to protect against electrostatic discharge (ESD) issues for high-speed ports. The device is also able to withstand IEC 61000-4-2 contact testing at ±14 kV and transmission line pulse (TLP) testing at 20 A. The device is fabricated using a typical planar Bipolar-CMOS-DMOS (BCD) process. By slotting the doping well to decrease the concentration of diodes, a TVS with an ultralow Cj is obtained without the need to add to the process procedures or without damaging the ESD capability. [ABSTRACT FROM PUBLISHER]

This letter demonstrates a successful method for ON-state resistance reduction up to 20% by Shallow Trench Isolation (STI) fingers and with extra NLDD implant in the fingered region simultaneously for medium power devices. This fingered region provides a multidimensional electric field that avoids MOSFET breakdown voltage decrease, and it also shortens the drain-current conduction path. Therefore, low ON-state resistance and high drain driving current is obtained in our proposed device. Careful design for structural parameters of this STI finger is needed to achieve the optimum RON performance without hurting breakdown voltage. [ABSTRACT FROM AUTHOR]

AlGaN/GaN dual metal Schottky barrier diodes (SBD) are demonstrated on a silicon substrate. The anode is composed of two metals with different work functions to achieve a better trade-off between the forward and the reverse characteristics. The low work function metal Ti reduces the turn-on voltage and the high work function metal Ni at the edge of the anode reduces the reverse leakage current and maintains the breakdown voltage. The turn-on voltage of the Ni-SBD is reduced from 1.47 V to 0.57 V by employing the dual metal anode, and the breakdown voltages are virtually unaffected. [ABSTRACT FROM AUTHOR]