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This article proposes a systematic synthesis method to identify the optimum converter topology for a specified voltage conversion ratio. This gain-oriented converter synthesis is formulated as an inverse problem around the inductor flux balance equations. The proposed synthesis method consists of two processes. A set of distinct converter topologies is first synthesized from the specified voltage conversion ratio by obtaining the solutions for a set of six inverse equations in twelve unknowns. The optimal topology for any intended application can be identified based on the desired performance metrics. The complete synthesis method is illustrated with quadratic buck–boost gain as an example. In total, 25 distinct topologies are synthesized using the first process, and their feasibility is validated by PLECS simulation. In total, three case studies are reported to explain the second process. Ground-referenced output and the minimum number of switches are used as the first two selection criteria in all the case studies. Minimum peak inductor current, minimum component stress factor, and minimum voltage and current stress are the third selection criterion in Case Studies-1, 2, and 3, respectively. The steady-state operations of two optimal converters selected in Case Study-1 were verified experimentally. [ABSTRACT FROM AUTHOR]

This article presents an analytical method to derive an optimum converter topology for a specified voltage conversion ratio (G). An optimum topology for any given G can be identified after obtaining the comprehensive pool of converter topologies. This gain-oriented converter synthesis is formulated as an inverse problem around the principle of inductor flux balance. A step-by-step method is proposed to solve the inverse problem and obtain a comprehensive set of non-redundant converter topologies for any given voltage conversion ratio. Consequently, the number of possible converter topologies for a specified voltage conversion ratio is also identified. The optimum converter topology is chosen from the comprehensive set based on three selection criteria, viz., ground-referenced output, a minimum number of switches, and minimum peak inductor current. The proposed solution methodology is illustrated with quadratic boost and quadratic buck gains as case studies. A comprehensive set of non-redundant topologies is identified in both cases. The steady-state operations of all the topologies are studied with PLECS simulation. Based on the selection criteria, an optimum topology is selected in each case, and their steady-state operation is verified experimentally using lab-developed prototypes. [ABSTRACT FROM AUTHOR]

Impedance source inverters (ISIs) are gaining attention due to features such as single-stage conversion, buck-boost capability, and inherent shoot-through protection. To maintain the required ac output voltage, typically ISIs are operated at a higher dc-link voltage due to constrained modulation index. This also increases voltage stress across capacitors and switches of the converter. This voltage stress is approximately double compared to that of voltage source inverter with preboost stage (Boost-VSI). To mitigate this problem, a new pulsewidth modulation (PWM) scheme for the active-front-end based ISIs (AFE-ISIs) is proposed. The proposed scheme enables the ISIs to produce high ac gain with lower voltage stress across the capacitor and switches. In other words, the proposed scheme blends the advantages of Boost-VSI into ISIs. With the new PWM scheme, there are also reductions in output voltage total harmonic distortion, switching frequency ripple in the inductor current, and power loss in the converter. A prototype of the current-fed switched inverter, an AFE-ISI, is designed, and the proposed PWM scheme is implemented. Experimental results obtained are in accordance with the proposed theory and show that the voltage stress has reduced from 325 V to 203 V for an ac output of 110 V. [ABSTRACT FROM AUTHOR]

The Z-source inverter (ZSI) employs an LC impedance network between the main inverter bridge and the power source. The unique feature of the ZSI is that it can operate either in buck or boost mode with a wide range of obtainable output voltages from a given input voltage. This topology also exhibits better electromagnetic-interference noise immunity when compared to a traditional voltage-source inverter (VSI). However, the LC impedance network of ZSI significantly increases the size and cost of the power converter and can make it unsuitable for low-power applications. This paper proposes a novel topology called switched boost inverter (SBI) which exhibits similar advantages of ZSI with lower number of passive components and more active components compared to ZSI. The steady-state and small-signal analyses of SBI, along with its pulsewidth modulation (PWM) control strategies, have been discussed in this paper. This paper also presents a comparison of SBI and ZSI with the same input and output parameters. The theoretical analysis given in this paper has been validated using a laboratory prototype of SBI, and the experimental results are presented for verification. The experimental harmonic spectrum of the inverter's output voltage with the proposed PWM technique is also plotted and compared with that of a traditional VSI. All the experimental results show good correlation between theory and experiments. [ABSTRACT FROM PUBLISHER]

Abstract-Hysteretic modulators have superior dynamic performance, and they also help reduce the number of output capacitors without sacrificing the transient response. For proper hysteretic operation, the voltage ripple is required to be piecewise linear and noise free. With modern computational integrated circuits lower supply voltage with tight regulation requirements, the output voltage ripple is both small and noisy. The synthetic ripple modulator (SRM) allows proper hysteretic operation even with a small and corrupted output voltage ripple. This paper discusses the dynamic behavior of the SRM. Small-signal characteristics of the modulator are derived. An easy-to-use numerically efficient model has been developed to accurately predict the smalland large-signal behavior of the converter driven by the SRM. The model is able to predict the small-signal behavior of the SRM up to half the switching frequency with sufficient accuracy. It can predict the same large-signal responses as real-time simulation, but at two orders of magnitude less in computation time. Laboratory tests on a 1.8 V/20 A single-phase prototype shows good correlation between experimental results and theoretical predictions both in frequency and time domain. [ABSTRACT FROM AUTHOR]