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A ferroelectric FET using MoS2 and PVDF-TrFE was fabricated, and the effects of varying the gate voltage scan rate from 200 mV/s to 4 mV/s investigated. Charge mobility, sub-threshold voltage swing and the memory window width depended on the scan rate. Prior to switching on, a negative trans-conductance was observed for all scan rates, followed by a rapid increase in the channel current to the on state. A model based on nucleation of ferroelectric domains and unrestricted domain growth was used to explain these results. By lowering the scan rate, the performance of polymer based FE-FET's can be improved. [ABSTRACT FROM AUTHOR]