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In this paper, we report the first systematic study of quantum transport simulation of the impact of precisely positioned dopants on the performance of ultimately scaled gate-all-around silicon nanowire transistors (NWTs) designed for digital circuit applications. Due to strong inhomogeneity of the self-consistent electrostatic potential, a full 3-D real-space nonequilibrium Green function formalism is used. The simulations are carried out for an n-channel NWT with \2.2 \times \2.2\ \nm^2 cross section and 6-nm channel length, where the locations of the precisely arranged dopants in the source–drain extensions and in the channel region have been varied. The individual dopants act as localized scatters, and hence, impact of the electron transport is directly correlated to the position of the single dopants. As a result, a large variation in the on-current and a modest variation of the subthreshold slope are observed in the ID–VG characteristics when comparing devices with microscopically different discrete dopant configurations. The variations of the current–voltage characteristics are analyzed with reference to the behavior of the transmission coefficients. [ABSTRACT FROM AUTHOR]

In this work we investigate the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future CMOS applications at the scaling limit. For the purpose of this paper, we created Si NWTs with two channel crystallographic orientations 〈1 1 0〉 and 〈1 0 0〉 and six different cross-section profiles. In the first part, we study the impact of quantum corrections on the gate capacitance and mobile charge in the channel. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic performance of the NWTs, is also investigated. The influence of the rotating of the NWTs cross-sectional geometry by 90° on charge distribution in the channel is also studied. We compare the correlation between the charge profile in the channel and cross-sectional dimension for circular transistor with four different cross-sections diameters: 5 nm, 6 nm, 7 nm and 8 nm. In the second part of this paper, we expand the computational study by including different gate lengths for some of the Si NWTs. As a result, we establish a correlation between the mobile charge distribution in the channel and the gate capacitance, drain-induced barrier lowering (DIBL) and the subthreshold slope (SS). All calculations are based on a quantum mechanical description of the mobile charge distribution in the channel. This description is based on the solution of the Schrödinger equation in NWT cross sections along the current path, which is mandatory for nanowires with such ultra-scale dimensions. [ABSTRACT FROM AUTHOR]