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Disentanglement of constituent factors of a sensory signal is central to perception and cognition and hence is a critical task for future artificial intelligence systems. In this paper, we present a compute engine capable of efficiently factorizing holographic perceptual representations by exploiting the computation-in-superposition capability of brain-inspired hyperdimensional computing and the intrinsic stochasticity associated with analog in-memory computing based on nanoscale memristive devices. Such an iterative in-memory factorizer is shown to solve at least five orders of magnitude larger problems that cannot be solved otherwise, while also significantly lowering the computational time and space complexity. We present a large-scale experimental demonstration of the factorizer by employing two in-memory compute chips based on phase-change memristive devices. The dominant matrix-vector multiply operations are executed at O(1) thus reducing the computational time complexity to merely the number of iterations. Moreover, we experimentally demonstrate the ability to factorize visual perceptual representations reliably and efficiently., 23 pages, 4 figures, 1 extended data figure, 3 supplementary notes, 2 supplementary figures and 3 supplementary tables

Broadband current sensors are key components in numerous applications, including power conversion, motor control, and smart-metering. We present a compressive sensing (CS) current sensor system-on-chip (SoC) designed and fabricated in STM 0.16 µm Bipolar-CMOS-DMOS technology. The SoC is capable of measuring currents with amplitudes of up to 10 A peak with a sensing bandwidth of 1 MHz. Two broadband current sensing cores, each consisting of a Hall-effect probe, an AFE, and a 2 MS/s 9-bit ADC, are monolithically integrated together with a digital multi-mode compressive sensing encoder (DCSE) for data-rate reduction. We focus on the evaluation of CS as data compression codec for current sensing applications and on the details of the DCSE architecture designed for general purpose use. We introduce multi-block decoding that is a decoding modality to improve the reconstruction quality of 'off-grid sparse' signals commonly occurring in practice. Moreover, we provide measurements of both the compression performance and power consumption of the SoC employed in two exemplary real-world applications; namely, sparse current sensing, and electrical appliance detection for non-intrusive load monitoring based on compressive measurements.

Energy efficiency is crucial in the design of battery-powered end devices, such as smart sensors for the Internet of Things applications. Wireless communication between these distributed smart devices consumes significant energy, and even more when data need to reach several kilometers in distance. Low-power and long-range communication technologies such as LoRaWAN are becoming popular in IoT applications. However, LoRaWAN has drawbacks in terms of (i) data latency, (ii) limited control over the end devices by the gateway, and (iii) high rate of packet collisions in a dense network. To overcome these drawbacks, we present an energy-efficient network architecture and a high-efficiency on-demand time-division multiple access (TDMA) communication protocol for IoT improving both the energy efficiency and the latency of standard LoRa networks. We combine the capabilities of short-range wake-up radios to achieve ultra-low power states and asynchronous communication together with the long-range connectivity of LoRa. The proposed approach still works with the standard LoRa protocol, but improves performance with an on-demand TDMA. Thanks to the proposed network and protocol, we achieve a packet delivery ratio of 100% by eliminating the possibility of packet collisions. The network also achieves a round-trip latency on the order of milliseconds with sensing devices dissipating less than 46 mJ when active and 1.83 &mu, W during periods of inactivity and can last up to three years on a 1200-mAh lithium polymer battery.

International audience; Wireless sensor nodes are traditionally powered by individual batteries, and a significant effort has been devoted to maximizing the lifetime of these devices. However, as the batteries can only store a finite amount of energy, the network is still doomed to die, and changing the batteries is not always possible. A promising solution is to enable each node to harvest energy directly in its environment, using individual energy harvesters. Moreover, novel ultra-low power wake-up receivers, which allow continuous listening of the channel with negligible power consumption, are emerging. These devices enable asynchronous communication, further reducing the power consumption related to communication, which is typically one the most energy-consuming tasks in wireless sensor networks. Energy harvesting and wake-up receivers can be combined to significantly increase the energy efficiency of sensor networks. In this paper, we propose an energy manager for energy harvesting wireless sensor nodes and an asynchronous medium access control protocol, which exploits ultra-low power wake-up receivers. The two components are designed to work together and especially to fit the stringent constraints of wireless sensor nodes. The proposed approach has been implemented on a real hardware platform and tested in the field. Experimental results demonstrate the benefits of the proposed approach in terms of energy efficiency, power consumption and throughput, which can be up to more than two-times higher compared to traditional schemes.

We report an always-on event-driven asynchronous wake-up circuit with trainable pattern recognition capabilities to duty-cycle power-constrained Internet-of-Things (IoT) sensor nodes. The wake-up circuit is based on a level-crossing analog-to-digital converter (LC-ADC) employed as a feature-extraction block with automatic activity-sampling rate scaling behavior. A novel asynchronous digital logic classifier for sequential pattern recognition is presented. It is driven by the LC-ADC activity and trained to minimize classification errors due to falsely detected events. As proof-of-concept, a prototype of the wake-up circuit is fabricated in 130nm CMOS technology within 0.054 mm2 of active area, covering up to 2.6 kHz of input signal bandwidth. The prototype has been first validated by interfacing it with a commercial accelerometer to classify hand gestures in real-time, reaching 81% of accuracy with only 2.2 μW at 1-V supply. To highlight the flexibility of the design, a second application, detecting pathologic electrocardiogram beats is also discussed.

This work presents a wearable EMG gesture recognition system based on the hyperdimensional (HD) computing paradigm, running on a programmable Parallel Ultra-Low-Power (PULP) platform. The processing chain includes efficient on-chip training, which leads to a fully embedded implementation with no need to perform any offline training on a personal computer. The proposed solution has been tested on 10 subjects in a typical gesture recognition scenario achieving 85% average accuracy on 11 gestures recognition, which is aligned with the State-Of-the-Art (SoA), with the unique capability of performing online learning. Furthermore, by virtue of the Hardware (HW) friendly algorithm and of the efficient PULP System-on-Chip (SoC) (Mr. Wolf) used for prototyping and evaluation, the energy budget required to run the learning part with 11 gestures is 10.04mJ, and 83.2uJ per classification. The system works with a average power consumption of 10.4mW in classification, ensuring around 29h of autonomy with a 100mAh battery. Finally, the scalability of the system is explored by increasing the number of channels (up-to 256 electrodes), demonstrating the suitability of our approach as universal, energy-efficient biopotential wearable recognition framework., IEEE Transactions on Biomedical Circuits and Systems, 13 (3), ISSN:1932-4545, ISSN:1940-9990

Energy harvesters are being used to power autonomous systems, but their output power is variable and intermittent. To sustain computation, these systems integrate batteries or supercapacitors to smooth out rapid changes in harvester output. Energy storage devices require time for charging and increase the size, mass, and cost of systems. The field of transient computing moves away from this approach, by powering the system directly from the harvester output. To prevent an application from having to restart computation after a power outage, approaches such as Hibernus allow these systems to hibernate when supply failure is imminent. When the supply reaches the operating threshold, the last saved state is restored and the operation is continued from the point it was interrupted. This paper proposes Hibernus++ to intelligently adapt the hibernate and restore thresholds in response to source dynamics and system load properties. Specifically, capabilities are built into the system to autonomously characterize the hardware platform and its performance during hibernation in order to set the hibernation threshold at a point which minimizes wasted energy and maximizes computation time. Similarly, the system auto-calibrates the restore threshold depending on the balance of energy supply and consumption in order to maximize computation time. Hibernus++ is validated both theoretically and experimentally on microcontroller hardware using both synthesized and real energy harvesters. Results show that Hibernus++ provides an average 16% reduction in energy consumption and an improvement of 17% in application execution time over state-of-the-art approaches.

A 4-core cluster fabricated in low power 28nm UTBB FD-SOI conventional well technology is presented. The SoC architecture enables the processors to operate 'on-demand' on a 0.44V (1.8MHz) to 1.2V (475MHz) supply voltage wide range and -1.2V to 0.9V body bias wide range achieving the peak energy efficiency of 60 GOPS/W, (419μW, 6.4MHz) at 0.5V with 0.5V forward body bias. The proposed SoC energy efficiency is 1.4x to 3.7x greater than other low-power processors with comparable performance.

Supply voltage (VDD) scaling offers a means to greatly reduce power in serial link transceivers. Ideally, power efficiency at a given data rate can be improved by reducing VDD while increasing the number of multiplexed circuits operating in parallel at lower clock frequencies [1]. Though increasing the amount of parallelism is desirable to scale VDD, in practice, it is limited by two main factors. First, increased sensitivity to device variations (threshold voltage/dimension mismatch) at lower VDD makes it extremely challenging to generate equally spaced multi-phase clocks needed in multiplexed transmitter and receiver. Phase calibration methods can correct phase-spacing errors [2,3], but their effectiveness at lower VDD is limited as the calibration circuits themselves become sensitive to device variations. Second, as oscillator output swing reduces with VDD, its phase noise degrades, making low-noise clock generation difficult to implement with low power dissipation. Phase noise can be suppressed by embedding the oscillator in a wide bandwidth analog phase-locked loop (APLL), but conventional charge-pump-based APLLs are difficult to design at low supply voltages (VDD DD, but they suffer from conflicting noise bandwidth tradeoffs, which prevent increasing the bandwidth to suppress oscillator phase noise adequately. In this paper, we present a phase-calibration method that enables the operation of a source-synchronous transceiver down to VDD of 0.45V. The energy efficiency and data-rate of the prototype transceiver scale from 0.29 to 0.58pJ/b and 1.3Gb/s to 6Gb/s, respectively, as VDD is varied from 0.45 to 0.7V.

Proceedings of the IEEE, 107 (1), ISSN:1558-2256, ISSN:0018-9219

We propose an intracranial electroencephalography (iEEG) based algorithm for detecting epileptic seizures with short latency, and with identifying the most relevant electrodes. Our algorithm first extracts three features, namely mean amplitude, line length, and local binary patterns that are fed to an ensemble of classifiers using hyperdimensional (HD) computing. These features are embedded into an HD space where well-defined vector-space operations are used to construct prototype vectors representing ictal (during seizures) and interictal (between seizures) brain states. Prototype vectors can be computed at different spatial scales ranging from a single electrode up to many electrodes covering different brain regions. This flexibility allows our algorithm to identify the iEEG electrodes that discriminate best between ictal and interictal brain states. We assess our algorithm on the SWEC-ETHZ iEEG dataset that includes 99 short-time iEEG seizures recorded with 36 to 100 electrodes from 16 drug-resistant epilepsy patients. Using k-fold cross-validation and all electrodes, our algorithm surpasses state-of-the-art algorithms yielding significantly shorter latency (8.81 s vs. 9.94 s) in seizure onset detection, and higher sensitivity (96.38 % vs. 92.72 %) and accuracy (96.85 % vs. 95.43 %). We can further reduce the latency of our algorithm to 3.74 s by allowing a slightly higher percentage of false alarms (2 % specificity loss). Using only the top 10 % of the electrodes ranked by our algorithm, we still maintain superior latency, sensitivity, and specificity compared to the other algorithms with all the electrodes. We finally demonstrate the suitability of our algorithm to deployment on low-cost embedded hardware platforms, thanks to its robustness to noise/artifacts affecting the signal, its low computational complexity, and the small memory-footprint on a RISC-V microcontroller.

Hand movement classification via surface electromyographic (sEMG) signal is a well-established approach for advanced Human-Computer Interaction. However, sEMG movement recognition has to deal with the long-term reliability of sEMG-based control, limited by the variability affecting the sEMG signal. Embedded solutions are affected by a recognition accuracy drop over time that makes them unsuitable for reliable gesture controller design. In this paper, we present a complete wearable-class embedded system for robust sEMG-based gesture recognition, based on Temporal Convolutional Networks (TCNs). Firstly, we developed a novel TCN topology (TEMPONet), and we tested our solution on a benchmark dataset (Ninapro), achieving 49.6% average accuracy, 7.8%, better than current State-Of-the-Art (SoA). Moreover, we designed an energy-efficient embedded platform based on GAP8, a novel 8-core IoT processor. Using our embedded platform, we collected a second 20-sessions dataset to validate the system on a setup which is representative of the final deployment. We obtain 93.7% average accuracy with the TCN, comparable with a SoA SVM approach (91.1%). Finally, we profiled the performance of the network implemented on GAP8 by using an 8-bit quantization strategy to fit the memory constraint of the processor. We reach a $\mathbf {4\times }$ lower memory footprint (460 kB) with a performance degradation of only 3% accuracy. We detailed the execution on the GAP8 platform, showing that the quantized network executes a single classification in 12.84 ms with a power envelope of 0.9 mJ, making it suitable for a long-lifetime wearable deployment.

We report VivoSoC , a system-on-chip realized in 130-nm CMOS for miniaturized medical instrumentation as used in mobile health devices or implantable telemetry systems for animal experiments. It features six neural stimulation channels and acquisition circuits for 9 $\times $ electrode-based recordings, 4-channel/32-LED photoplethysmography (PPG), bioimpedance, and temperature. A 34- $\mu \text{W}$ /MHz quad-core processing unit with sophisticated data, power, and clock management techniques enables on-chip feature extraction, which can dramatically reduce transmission or storage data rates in a system—crucial for overall power consumption and exemplarily demonstrated on preliminary work on implantable PPG-based vital signs monitoring.

IEEE Transactions on Instrumentation and Measurement, 67 (4), ISSN:0018-9456, ISSN:1557-9662

A low-power source-synchronous multi-Gb/s transceiver is presented. Supply voltage is aggressively scaled to reduce power, and the speed penalty resulting from low-voltage operation is overcome by multiplexing transmitter/receiver synchronized by low-rate multi-phase clocks. Phase spacing errors incurred by device mismatches are corrected using a self-calibration scheme. The proposed phase calibration method uses a single digital DLL to calibrate all the phases, which makes it insensitive to offsets in the calibrating DLL. Fabricated in a 65-nm CMOS process, energy efficiency and data rate of the prototype transceiver vary from 0.29 to 0.58 pJ/bit and 1 to 6 Gb/s, respectively, as the supply voltage changes from 0.45 to 0.7 V.

Convolutional neural networks (CNNs) have revolutionized the world of computer vision over the last few years, pushing image classification beyond human accuracy. The computational effort of today’s CNNs requires power-hungry parallel processors or GP-GPUs. Recent developments in CNN accelerators for system-on-chip integration have reduced energy consumption significantly. Unfortunately, even these highly optimized devices are above the power envelope imposed by mobile and deeply embedded applications and face hard limitations caused by CNN weight I/O and storage. This prevents the adoption of CNNs in future ultralow power Internet of Things end-nodes for near-sensor analytics. Recent algorithmic and theoretical advancements enable competitive classification accuracy even when limiting CNNs to binary (+1/−1) weights during training. These new findings bring major optimization opportunities in the arithmetic core by removing the need for expensive multiplications, as well as reducing I/O bandwidth and storage. In this paper, we present an accelerator optimized for binary-weight CNNs that achieves 1.5 TOp/s at 1.2 V on a core area of only 1.33 million gate equivalent (MGE) or 1.9 mm 2 and with a power dissipation of 895 $\mu$ W in UMC 65-nm technology at 0.6 V. Our accelerator significantly outperforms the state-of-the-art in terms of energy and area efficiency achieving 61.2 TOp/s/W@0.6 V and 1.1 TOp/s/MGE@1.2 V, respectively.

IEEE Transactions on Circuits and Systems for Video Technology, 27 (11), ISSN:1051-8215, ISSN:1558-2205

Duty-cycled low-rate Internet-of-things (IoT) sensors are employed in diverse applications, requiring configurable and energy-efficient on-chip and on-demand clock synthesis. We present an all-digital frequency-locked loop (AD-FLL) capable of generating an accurate clock selectively in stand-alone operation or locked to a 32kHz reference. We report measurement results of two prototypes in 65nm and 28nm CMOS offering a configurable clock multiplication factor of up to 32 786, resulting in a wide tuning-range from a few MHz to 2.4GHz and 1.6GHz, respectively. The challenges of slow start-up and deterministic jitter are addressed by a fast hybrid-mode start-up procedure and by various jitter reduction modes. We also introduce the concept of Transient Clocking that leverages the capabilities of the proposed AD-FLL to make a system operational after cold-start or wake-up before the supply voltage has stabilized. We study two application examples that highlight the versatility of the concept in IoT applications and show its potential to amortize the time and energy cost of typical system start-up tasks, like state-restoration or wake-up event classification.

This article presents an ultra-low-power parallel computing platform and its system-on-chip (SoC) embodiment, targeting a wide range of emerging near-sensor processing tasks for Internet of Things (IoT) applications. The proposed SoC achieves 193 million operations per second (MOPS) per mW at 162 MOPS (32 bits), improving the first-generation Parallel Ultra-Low-Power (PULP) architecture by 6.4 and 3.2 times in performance and energy efficiency, respectively.

Hybrid memory cube (HMC) has promised to improve bandwidth, power consumption, and density for the next-generation main memory systems. In addition, 3-D integration gives a second shot for revisiting near memory computation to fill the gap between processors and memories. In this paper, we study the required infrastructure inside the HMC to support near memory computation in a modular and flexible fashion. We propose a fully backward compatible extension to the standard HMC called the smart memory cube, and design a high bandwidth, low latency, and Advanced eXtensible Interface-4.0 compatible logic base (LoB) interconnect to serve the huge bandwidth demand by the HMCs serial links, and to provide extra bandwidth to a generic processor-in-memory (PIM) device embedded in the LoB. This interconnect features a novel address scrambling mechanism for the reduction in the vault/bank conflicts and robust operation even in the presence of pathological traffic patterns. Our cycle accurate simulation results demonstrate that this interconnect can easily meet the demands of the latest HMC specifications (up to 205 GB/s read bandwidth with 4 serial links and 32 memory vaults for injected random traffic). It further shown that the default addressing scheme of the HMC (low interleaving) is not reliable enough and operates poorly in the presence of specific traffic patterns from real applications. This is while the proposed scrambling mechanism operates robustly even in those cases. The interference between the PIM traffic and the main links is shown to be negligible when the number of PIM ports is limited to 2, requesting up to 64 GB/s without pushing the system into saturation. Finally, logic synthesis with Synopsys Design Compiler confirms that our interconnect is implementable and effective in terms of power, area, and timing (power consumption less than 5 mW up to 1 GHz and area less than 0.4 mm²).

To enable pervasive exploitation of wireless sensor networks (WSNs), semi-passive wake-up radios (WuR) are proposed to minimize the active time of the energy-hungry main communication radio. The most challenging feature is to enhance their sensitivity, the weakest activation signal the receiver is able to sense, that is limited by the minimum turn-on voltage of diode-based detector. In order to operate the detector at even lower power levels, a strategy to optimize the modulated WuR excitations is presented, exploiting high-peak intermittent continuous waves (ICW), while preserving the required average power per bit. The design and implementation of an ultra-low-power detector, fed by a dual-band antenna and loaded by the WuR back-end is presented: 2.45-GHz and 868-MHz operations of the same WuR are demonstrated, with added flexibility and interoperability among different communication bands. We show that a correct WuR activation is possible with an average power per bit as low as -63 dBm at 2.45 GHz and -65 dBm at 868 MHz. This is experimentally verified by a lab-level set-up and confirmed by a system implementation based on off-the-shelf components only.

In this paper, we give a fresh look to coarse grained reconfigurable arrays (CGRAs) as ultralow power accelerators for near-sensor processing. We present a general-purpose integrated programmable-array accelerator (IPA) exploiting a novel architecture, execution model, and compilation flow for application mapping that can handle kernels containing complex control flow, without the significant energy overhead incurred by state of the art predication approaches. To optimize the performance and energy efficiency, we explore the IPA architecture with special focus on shared memory access, with the help of the flexible compilation flow presented in this paper. We achieve a maximum energy gain of $2{\times }$ , and performance gain of $1.33{\times }$ and $1.8{\times }$ compared with state of the art partial and full predication techniques, respectively. The proposed accelerator achieves an average energy efficiency of 1617 MOPS/mW operating at 100 MHz, 0.6 V in 28 nm UTBB FD-SOI technology, over a wide range of near-sensor processing kernels, leading to an improvement up to $18{\times }$ , with an average of $9.23{\times }$ (as well as a speed-up up to $20.3{\times }$ , with an average of $9.7{\times }$ ) compared to a core specialized for ultralow power near-sensor processing.

LoRaWAN is one of the most promising standards for long-range sensing applications. However, the high number of end devices expected in at-scale deployment, combined with the absence of an effective synchronization scheme, challenge the scalability of this standard. In this paper, we present an approach to increase network throughput through a Slotted-ALOHA overlay on LoRaWAN networks. To increase the single channel capacity, we propose to regulate the communication of LoRaWAN networks using a Slotted-ALOHA variant on the top of the Pure-ALOHA approach used by the standard; thus, no modification in pre-existing libraries is necessary. Our method is based on an innovative synchronization service that is suitable for low-cost wireless sensor nodes. We modelled the LoRaWAN channel with extensive measurement on hardware platforms, and we quantified the impact of tuning parameters on physical and medium access control layers, as well as the packet collision rate. Results show that Slotted-ALOHA supported by our synchronization service significantly improves the performance of traditional LoRaWAN networks regarding packet loss rate and network throughput., Sensors, 19 (4), ISSN:1424-8220

Smart building applications require a large-scale deployment of sensors distributed across the environment. Recent innovations in smart environments are driven by wireless networked sensors as they are easy to deploy. However, replacing these batteries at scale is a non-trivial, labor-intensive task. Energy harvesting has emerged as a potential solution to avoid battery replacement but requires compromises such as application specific design, simplified communication protocol or reduced quality of service. We explore the design space of battery-free sensor nodes using commercial off the shelf components, and present Pible: a Perpetual Indoor BLE sensor node that leverages ambient light and can support numerous smart building applications. We analyze node-lifetime, quality of service and light availability trade-offs and present a predictive algorithm that adapts to changing lighting conditions to maximize node lifetime and application quality of service. Using a 20 node, 15-day deployment in a real building under varying lighting conditions, we show feasible applications that can be implemented using Pible and the boundary conditions under which they can fail., 4 pages, 4 figures, BuildSys '18: Conference on Systems for Built Environments, November 7--8, 2018, Shenzen, China

Structural health monitoring (SHM) systems are becoming increasingly widespread and are in some cases mandated by law. A major factor limiting the diffusion of such systems is the lack of low-cost low-power sensor nodes, which can be deployed in large numbers in hard-to-reach areas, while providing high-quality precise measurements over their entire lifespan with minimum maintenance and withstanding climatic stress. In this paper, we present a cost-effective wireless component for Structural Health Monitoring (SHM) that measure and track cracks in concrete and other construction materials. The sensor combines a microprocessor with LoRaWAN wireless communication, an analog transducer, and a solar energy harvester, allowing long-term remote monitoring with easy plug and play installation. Experimental results demonstrate that we achieved about ${1\mu\mathrm{m}}$ accuracy and an expected lifetime of more than 10 years, with stable measurements across a-IS – 65°C temperature range.

Variation in performance and power across manufactured parts and their operating conditions is an accepted reality in modern microelectronic manufacturing processes with geometries in nanometer scales. This article surveys challenges and opportunities in identifying variations, their effects and methods to combat these variations for improved microelectronic devices. We focus on computing devices and their design at various levels to combat variability. First, we provide a review of key concepts with particular emphasis on timing errors caused by various variability sources. We consider methods to predict and prevent, detect and correct, and finally conditions under which such errors can be accepted; we also consider their implications on cost, performance and quality. We provide a comparative evaluation of methods for deployment across various layers of the system from circuits, architecture, to application software. These can be combined in various ways to achieve specific goals related to observability and controllability of the variability effects, providing means to achieve cross-layer or hybrid resilience. We then provide examples of real world resilient single-core and parallel architectures. We find that parallel architectures and parallelism in general provide the best means to combat and exploit variability to design resilient and efficient systems. Using programmable accelerator architectures such as clustered processing elements and GP-GPUs, we show how system designers can coordinate propagation of timing error information and its effects along with new techniques for memoization (i.e., spatial or temporal reuse of computation). This discussion naturally leads to use of these techniques into emerging area of "approximate computing," and how these can be used in building resilient and efficient computing systems. We conclude with an outlook for the emerging field.

Mobile and long-term recording of biomedical signals, such as electrocardiogram (ECG), electromyogram (EMG), and EEG, can improve diagnosis and monitor the evolution of several widespread diseases. However, it requires specific solutions, such as wearable devices, that should be particularly comfortable for patients, while at the same time ensuring medical-grade signal acquisition quality, including power line interference (PLI) removal. This paper focuses on the on-board real-time PLI filtering on a low-power biopotential acquisition wearable system. This paper analyzes in depth basic and advanced PLI filtering techniques and evaluates them in a wearable real-time processing scenario, assessing performance on EMG and ECG signals. Our experiments prove that most PLI removal algorithms are not usable in this challenging context, because they lack robustness or they require offline processing and large amounts of available data. On the other hand, adaptive filtering techniques are robust and well suited for lightweight online processing. We substantiate this finding with offline analysis and comparison, as well as with a complete embedded implementation on our low-power low-cost wearable device.

Self-heating and high-operating temperature are major concerns in 3-D-chip integration. In this paper, we leverage a 3-D test chip (WideIO dynamic random access memory on top of a logic die) equipped with temperature sensors and heaters to explore thermal effects and to develop advanced thermal modeling strategies suitable for complex 3-D-stacked circuits. We correlate temperature measurements with the power dissipated by the heaters using model learning techniques. Moreover, we defined a thermal basis function obtained using power and thermal data available from the on-chip sensors. This function can be used to predict temperatures at chip locations far from the temperature sensors and to infer the power dissipation at any location of the chip. In addition, the same thermal basic function can be used jointly with formal interpolation frameworks like radial basis function methods to effectively estimate the full-chip thermal map. Results show that this methodology outperforms existing interpolation approaches for sparse integrated sensors.

Wireless sensor networks (WSNs) have received significant attention in recent years and have found a wide range of applications, including structural and environmental monitoring, mobile health, home automation, Internet of Things, and others. As these systems are generally battery operated, major research efforts focus on reducing power consumption, especially for communication, as the radio transceiver is one of the most power-hungry components of a WSN. Moreover, with the advent of energy-neutral systems, the emphasis has shifted toward research in microwatt (or even nanowatt) communication protocols or systems. A significant number of wake-up radio receiver (WUR) architectures have been proposed to reduce the communication power of WSN nodes. In this work, we present an optimized ultra-low power (nanowatt) wake-up receiver for use in WSNs, designed with low-cost off-the-shelf components. The wake-up receiver achieves power consumption of 152 nW (with $-32\,{\text {dBm}}$ sensitivity), sensitivity up to $-55\,{\text {dBm}}$ (with maximum power of $1,2 \upmu{\text {W}}$ ), latency from $8\;\upmu\text{s}$ , tunable frequency, and short commands communication. In addition, a low power solution, which includes addressing capability directly in the wake-up receiver, is proposed. Experimental results and simulations demonstrate low power consumption, functionality, and benefits of the design optimization compared with other solutions, as well as the benefits of addressing false positive (FP) outcomes reduction.

Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas, such as E-health, Internet of Things, and wearable Human–Computer Interfaces. A promising approach to achieve up to one order of magnitude of improvement in energy efficiency over current generation of integrated circuits is near-threshold computing. However, frequency degradation due to aggressive voltage scaling may not be acceptable across all performance-constrained applications. Thread-level parallelism over multiple cores can be used to overcome the performance degradation at low voltage. Moreover, enabling the processors to operate on-demand and over a wide supply voltage and body bias ranges allows to achieve the best possible energy efficiency while satisfying a large spectrum of computational demands. In this work we present the first ever implementation of a 4-core cluster fabricated using conventional-well 28 nm UTBB FD-SOI technology. The multi-core architecture we present in this work is able to operate on a wide range of supply voltages starting from 0.44 V to 1.2 V. In addition, the architecture allows a wide range of body bias to be applied from −1.8 V to 0.9 V. The peak energy efficiency 60 GOPS/W is achieved at 0.5 V supply voltage and 0.5 V forward body bias. Thanks to the extended body bias range of conventional-well FD-SOI technology, high energy efficiency can be guaranteed for a wide range of process and environmental conditions. We demonstrate the ability to compensate for up to 99.7% of chips for process variation with only ±0.2 V of body biasing, and compensate temperature variation in the range −40 °C to 120 °C exploiting −1.1 V to 0.8 V body biasing. When compared to leading-edge near-threshold RISC processors optimized for extremely low power applications, the multi-core architecture we propose has 144× more performance at comparable energy efficiency levels. Even when compared to other low-power processors with comparable performance, including those implemented in 28 nm technology, our platform provides 1.4× to 3.7× better energy efficiency.

Micro-energy harvesting from environmental sources is a promising technology for mobile or unobtrusive battery powered Internet of Things devices with constrains in terms of size and weight. Special integrated circuits aim to manage the voltage matching and power control in between the energy harvesting transducer and the storage. Hence, models to simulate the energy behaviour of these systems are important tools for system engineers. In this paper, a neuronal network model is presented to predict the performance of two state-of-the-art integrated circuits. Required model inputs are voltage and current from the energy harvesting transducer and the voltage level of the storage element. Model provides conversion efficiency as its output. Three different datasets have been collected with in-field experiments to build and evaluate the proposed model. Evaluation of the developed model on all datasets shows efficiency prediction root mean square error of less than 2 %.

Energy efficiency is a crucial aspect in modern SoCs. Common strategies like aggressive voltage scaling and parallel processing have enabled major improvements in active energy efficiency. However, the big impact of process variations, as well as the temperature sensitivity of devices operating in near threshold force digital designers to adopt very conservative margins for timing closure.

Ultralow-power embedded systems have recently started the move to multicore designs. Aggressive voltage scaling techniques have the potential to reduce the power consumption within the admitted envelope, but memory operations on standard six-transistor static RAM (6T-SRAM) cells become unreliable at low voltages. While standard cell memory (SCM) overcomes this limitation, it has much lower area density than SRAM, and thus it is too costly. On the other hand, several applications have inherent tolerance to computation errors, and executing such workloads with approximation has already proven a viable way to reduce energy consumption. In this paper, we propose a novel HW/SW approach to design energy-efficient ultralow-power systems which combine the key ideas of approximate computing and hybrid memory systems featuring both SCM and 6T-SRAM. We introduce a novel hardware support to split error-tolerant data so to host most significant bits in the SCM and least significant bits (LSBs) in the 6T-SRAM. This allows to power the memory system at a low voltage while ensuring correct operation by binding possible (flip-bit) errors to the LSBs only. In addition, by organizing 6T-SRAM banks into multiple and independent voltage domains we enable fine-grained, software-controlled voltage switching policies. At the software level, we propose language constructs to specify what regions of code and what variables are tolerant to approximation, plus compiler support to optimize data placement. Experimental results show that our proposal can reduce the energy consumption of the memory system by 47% on average, always complying with the result accuracy required by practical applications constraints.

For wearable devices, the availability of energy is one of the main limiting factors of performance and lifetime. To overcome this issue, micro-energy harvesting circuits, which extract energy from the environment, are very promising. Among other environmental sources, kinetic energy could significantly improve the energy availability in wearable applications. However, the majority of kinetic energy harvesting circuits do not perform well with the low-frequency patterns found in human motion and are therefore not suited for wearable devices. This paper aims to overcome this limitation by developing a high-efficiency energy harvesting system, which is optimized for frequencies occurring in human motion. A Micro Generator System (MGS) 26.4, by Kinetron, has been exploited as a kinetic transducer to generate energy. The implemented kinetic harvesting system has been designed to maximize the energy conversion efficiency and supply and recharge wearable devices. The final design has been implemented and field-tested in different positions on the human body. Experimental measurements demonstrate the end-to-end efficiency of up to 84%, and an average power of up to $\mathbf{624\mu W}$ , which is superior to the state-of-art for the type of MGS. Moreover, a preliminary evaluation of the correlation between acceleration and power harvested is presented. Using the values obtained from experimental data, we estimate that two hours of walking and 30 minutes of running per day can provide 1.4 joules of electrical energy.

2018 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), ISBN:978-1-5386-6103-1, ISBN:978-1-5386-6102-4, ISBN:978-1-5386-6104-8

IEEE Transactions on Circuits and Systems II. Express Briefs, 65 (8), ISSN:1549-7747, ISSN:1057-7130, ISSN:1558-3791, ISSN:1558-125X

We present an unobtrusive and minimally invasive system for acquiring 8-channels of EEG behind the ear, to support brain activity monitoring in a socially acceptable fashion and outside clinical environments. Electrical performance are in line with those of clinical EEG systems (0.48 µV RM S integrated noise in the [0-100] Hz band, 106 dB CMRR) and setup is extremely fast, requiring only a mild cleaning of the skin before applying the device. The system can acquire typical brain activity rhythms and potentials evoked by sensory stimuli, which are at the basis of BCI systems. Current consumption is 6.2 rnA, plus 16 mA for Bluetooth® data transmission (4.5 hours life on a 100 mAh battery). The overall cost of components is below 50 USD.

This paper presents a low-cost system that permits to provide structural modal analysis from a number of synchronized MEMS accelerometers distributed along the structure. The communication and computational effort is distributed among the nodes and data are provided real-time. Synchronization between sensors and accuracy of the measures permit to elaborate detailed modal analysis of the buildings. Experiments on real testbeds and structures demonstrate that the accuracy of the modal analysis is similar to the simulations executed using the models of the structures, and confirm that complex structural health evaluations are possible from a set of low-cost sensors.

This paper presents an efficient binarized algorithm for both learning and classification of human epileptic seizures from intracranial electroencephalography (iEEG). The algorithm combines local binary patterns with brain-inspired hyperdimensional computing to enable end-to-end learning and inference with binary operations. The algorithm first transforms iEEG time series from each electrode into local binary pattern codes. Then atomic high-dimensional binary vectors are used to construct composite representations of seizures across all electrodes. For the majority of our patients (10 out of 16), the algorithm quickly learns from one or two seizures (i.e., one-/few-shot learning) and perfectly generalizes on 27 further seizures. For other patients, the algorithm requires three to six seizures for learning. Overall, our algorithm surpasses the state-of-the-art methods [1] for detecting 65 novel seizures with higher specificity and sensitivity, and lower memory footprint., 2018 IEEE Biomedical Circuits and Systems Conference (BioCAS), ISBN:978-1-5386-3603-9, ISBN:978-1-5386-3604-6

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37 (11), ISSN:0278-0070, ISSN:1937-4151

EMG-based gesture recognition shows promise for human-machine interaction. Systems are often afflicted by signal and electrode variability which degrades performance over time. We present an end-to-end system combating this variability using a large-area, high-density sensor array and a robust classification algorithm. EMG electrodes are fabricated on a flexible substrate and interfaced to a custom wireless device for 64-channel signal acquisition and streaming. We use brain-inspired high-dimensional (HD) computing for processing EMG features in one-shot learning. The HD algorithm is tolerant to noise and electrode misplacement and can quickly learn from few gestures without gradient descent or back-propagation. We achieve an average classification accuracy of 96.64% for five gestures, with only 7% degradation when training and testing across different days. Our system maintains this accuracy when trained with only three trials of gestures; it also demonstrates comparable accuracy with the state-of-the-art when trained with one trial.

Recurrent neural networks (RNNs) are state-of-the-art in voice awareness/understanding and speech recognition. On-device computation of RNNs on low-power mobile and wearable devices would be key to applications such as zero-latency voice-based human-machine interfaces. Here we present CHIPMUNK, a small (, 2018 IEEE Custom Integrated Circuits Conference (CICC), ISBN:978-1-5386-2483-8, ISBN:978-1-5386-2482-1, ISBN:978-1-5386-2484-5

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), ISBN:978-1-5386-7099-6

Supercomputer installed capacity worldwide increased for many years and further growth is expected in the future. The next goal for high performance computing (HPC) systems is reaching Exascale. The increase in computational power threatens to lead to unacceptable power demands, if future machines will be built using current technology. Therefore reducing supercomputer power consumption has been the subject of intense research. A common approach to curtail the excessive power demands of supercomputers is to hard-bound their consumption, power capping. Power capping can be enforced by reactively throttling system performance when the power bound is hit, or by scheduling workload in a proactive fashion to avoid hitting the bound. In this paper we explore the second approach: our scheduler meets power capping constraints and minimizes quality-of-service (QoS) disruption through smart planning of the job execution order. The approach is based on constraint programming in conjunction with a machine learning module predicting the power consumptions of HPC applications. We evaluate our method on the Eurora supercomputer, using both synthetic workloads and historical traces. Our approach outperforms the state-of-the-art power capping techniques in terms of waiting time and QoS, while keeping schedule computation time under control.

We present Mr. Wolf, a Parallel Ultra Low Power (PULP) SoC featuring a hierarchical architecture with a small (12KG) microcontroller class RISC-V core augmented with an autonomous IO subsystem for efficient data transfer from a wide set of peripherals. The small core can offload compute-intensive kernels to an 8-cores floating-point capable processing engine available on demand. The proposed SoC, implemented in a 40 nm LP CMOS technology, features a 108 µW fully retentive memory (512 kB). The IO subsystem is capable of transferring up to 1.6Gbit/s in less than 2.5mW. The 8-core compute cluster achieves a peak performance of 850 millions of 32-bit integer multiply and accumulate per second (MMAC/s), 500 millions of 32-bit floating-point multiply and accumulate per second (MFMAC/s)-1 GFLOP/s - with an energy-efficiency up to 15 MMAC/s/mW and 9 MFMAC/s/mW. These building blocks are supported by aggressive on-chip power conversion and management, enabling energy-proportional heterogeneous computing for always-ON IOT end-nodes improving performance by several orders of magnitude with respect to traditional single core MCUs within a power envelope of 153 mW.

To overcome the limitations of conventional floating-point number formats, an interval arithmetic and variable-width storage format called universal number (unum) has been recently introduced [1]. This paper presents the first (to the best of our knowledge) silicon implementation measurements of an application-specific integrated circuit (ASIC) for unum floating-point arithmetic. The designed chip includes a 128-bit wide unum arithmetic unit to execute additions and subtractions, while also supporting lossless (for intermediate results) and lossy (for external data movements) compression units to exploit the memory usage reduction potential of the unum format. Our chip, fabricated in a 65 nm CMOS process, achieves a maximum clock frequency of 413 MHz at 1.2 V with an average measured power of 210uW/MHz.

Measuring radiation dosage rates is becoming more and more important in many applications scenarios. Continuously monitoring radiation in contaminated and poorly accessible areas is challenging due to the frequent data collection/transmission combined with long life requirements. We present a self-sustainable wireless sensor node for low power, high precision radiation dosage rate monitoring. We propose an energy-efficient data acquisition algorithm that can reduce the energy per measurement, while guaranteeing minimal loss of precision. The proposed node is designed to work in collaboration with an unmanned aerial vehicle used for two essential mission steps: air-deployment of the wireless sensor nodes at suitable locations, and acquiring data logs via low-power, short-range radio communication in fly-by mode after a wake-up command. The system uses off-the-shelf components for defining the mission, drop-zone, and trajectory, for compressing data and managing communication. The node is equipped with a novel low-power nuclear radiation sensor, and has been designed and implemented with self-sustainability in mind as it will be deployed in hazardous, inaccessible areas. To this end, the proposed node uses a combination of complementary techniques: a low-power microcontroller with non-volatile memory, energy harvesting, adaptive power management, and a nano-watt wake-up radio. Experimental results demonstrate the precision and the low energy consumption of the radiation sensor, the energy efficiency of the whole solution, and the acquisition algorithms. The node consumes only 31 $\mu \text{W}$ in sleep mode and 1.7mW in active mode, and has the capability to achieve perpetual monitoring once deployed.

Electronic skin (e-skin) is playing a key role in medicine, prosthetic and robot applications. E-skin tries to sense the world like the human skin does, exploiting arrays of sensors that produce a huge amount of data to be processed. Processing tactile data close to the e-skin imposes big challenges in terms of energy efficiency and real-time functionality. Energy efficient is particularly important for wearable and prosthetic applications where e-skin is mainly used as a wearable device supplied by battery. The major challenges it to find a sweet spot between power consumption and performance as tactile data decoding implementation requires high amount of computational power. This paper presents the hardware-software implementation of a complete low power embedded system that matches the computational requirements and the energy efficiency exploiting an ultralow power parallel processor. Tactile data decoding is directly performed on the embedded system, with a support vector machine (SVM) based tensor kernel algorithm, which classifies the input touch modalities. The paper presents the implementation of the algorithm in details and the power performance of the whole system based on experimental evaluation. Experimental results show that the energy efficiency is 9 times more than system based on a low power ARM-Cortex M4. Finally, the simulation on the energy consumption demonstrated that the developed system is able to last for 19.8 h in continuous mode with a single 2 Ah Lithium Polymer battery.

Editor’s note: As technology edges closer to fundamental limits, variations of process parameters, operational voltage, and temperature (PVT variations) have to be accounted for. This paper proposes to make higher levels aware of these variations and bring them under system control by using software controlled body biasing. PVT variations can thus be exploited to reduce power and energy consumption.— Axel Jantsch, TU Wien

The Internet of Things revolution requires long-battery-lifetime, autonomous end-nodes capable of probing the environment from multiple sensors and transmit it wirelessly after data-fusion, recognition, and classification. Duty-cycling is a well-known approach to extend battery lifetime: it allows to keep the hardware resources of the micro-controller implementing the end-node (MCUs) in sleep mode for most of the time, and activate them on-demand only during data acquisition or processing phases. To this end, most advanced MCUs feature autonomous I/O subsystems able to acquire data from multiple sensors when the CPU is in idle state. However, in these traditional I/O subsystems the interconnect is shared with the processing resources of the system, both converging in a single-port system memory. Moreover, both I/O and the data processing subsystems stand in some power domain. In this work we overcome the bandwidth and power-management limitations of current MCU’s I/O architectures introducing an autonomous I/O subsystem coupling an I/O DMA tightly-coupled with a multi-banked system memory controlled by a tiny CPU, which stands on a dedicated power domain. The proposed architecture achieves a transfer efficiency of 84% when considering only data transfers, and 53% if we consider also the overhead of the runtime running on the controlling processor, reducing the operating frequency of the I/O subsystem by up to 2.2x with respect to traditional MCU architectures.