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A calibration methodology for the optimized minimum inductor (OMI) bandpass filter (BPF) to compensate passive components' inherent loss, such as resistances and reactances, is presented. OMI BPF prevails conventional elliptic and Chebyshev BPFs by introducing fewer inductors for the same stopband rejection requirement. Given design specifications (bandwidth, stopband rejection) at a specific center frequency, the calibration flow optimizes the approach to offset the inaccuracy of center frequency, bandwidth, and stopband rejection due to the discrepancy between the actual and ideal prototype passive components. Two OMI BPF designs before and after calibration are presented for demonstration and comparison. They are 1) a 3rd order centered at 2.388 GHz, 35.54% fractional bandwidth (FBW), 29.97 dB stopband rejection, and 2) a 7th order centered at 2.333 GHz, 17.40% FBW, 62.29 dB stopband rejection.

In electronic-warfare (EW) receiver applications, real-time measurement of the radar signals' carrier frequencies is mandatory and considered to be one of the most important radar parameters. Accurate frequency detection can be used to sort and deinterleave signals in a dense signal environment where multiple signals arrive simultaneously presenting severe problems unless they can be differentiated appropriately. Researchers and engineers are actively looking for new algorithms for high resolution wideband receivers with easier implementation. This paper presents an adaptive gain control and dynamic thresholding wideband digital receiver to accurately detect two simultaneous high dynamic range signals, even when their signal frequencies are very close. The proposed fast Fourier transform (FFT) based receiver examines incoming signal characteristics and provides real-time accomplishment of these tasks, by way of using an adaptive gain-control amplifier, a squarer, two analog-to-digital converters, and two FFT's. The wideband receiver offers high probability of intercept over wide instantaneous RF bandwidths, high dynamic ranges and sensitivity. Two simultaneous signal accommodations and their characteristics are provided to demonstrate the improvements over presently used receivers in this field.

The use of chirp signals in modern radar and ranging systems have numerous benefits. They are extensively used to improve signal-to-noise ratio and range resolution. The performance capabilities of these signals are directly related to their time-bandwidth product, i.e., the duration and bandwidth of the pulse. Ultra-wideband chirp signals are further desirable because they span a large bandwidth, making them resistant to narrowband environmental interference. The accurate detection and measurement of high chirp signals is difficult due to the necessity of a high-sampling analog-digital converter, a target measurement platform with high computational power, and a time-of-arrival (TOA) estimator with high temporal resolution. The difficulty of the problem is further compounded with the requirement that no a priori knowledge of the signal, noise, or operating environment is known. This paper presents a practical approach and implementation of a high linear chirp rate receiver and TOA estimator pair capable of detecting and measuring stationary radio frequency pulses as well as linear chirp rates up to 1.18 GHz in 400 ns. The high-resolution TOA algorithm and linear chirp receiver have been prototyped, synthesized, and placed and routed for a Virtex 6 SX475 FPGA.

A classic second-order coupled-capacitor Chebyshev bandpass filter using resonator of tunable active capacitor and inductor is presented. The low cost and small size of CMOS active components make the bandpass filter (BPF) attractive in fully integrated CMOS applications. The tunable active capacitor is designed to compensate active inductor’s resistance for resistive match in the resonator. In many design cases, more than 95% resistive loss is cancelled. Meanwhile, adjusting design parameter of the active component provides BPF tunability in center frequency, pass band, and pass band gain. Designed in 1.8 V 180 nanometer CMOS process, the BPF has a tuning frequency range of 758–864 MHz, a controllable pass band of 7.1–65.9 MHz, a quality factor Q of 12–107, a pass band gain of 6.5–18.1 dB, and a stopband rejection of 38–50 dB.

Dynamic CMOS circuits are significantly used in high-performance very large-scale integrated (VLSI) systems. However, they suffer from limitations such as noise tolerance, charge leakage, and power consumption. With the escalating impact of process variations on design performance, aggressive technology scaling, noise in dynamic CMOS circuit has become an imperative design challenge. The design performance of dynamic circuits has to be first improved for reliable operation of VLSI systems. Alongside, this impact of process variation is worse in circuits with multiple timing paths such as those used in microprocessors. In this paper, these problems of process variations, timing, noise tolerance, and power are investigated together for performance optimization. We propose a process variation-aware load-balance of multiple paths transistor sizing algorithm to: 1) improve worst-case delay, delay uncertainty, and sensitivity due to process variations in dynamic CMOS circuits, and 2) optimize dynamic CMOS circuits with MOSFET-based keepers to improve the noise tolerance. Implemented using 90-nm CMOS process, the proposed algorithm has demonstrated an average improvement in worst-case delay by 34%, delay uncertainty by 40.3%, delay sensitivity by 25.1%, and noise margins by 19.4% when compared to their initial performances.

A primary concern in the current radar-receiver design involves the critical issue of setting a threshold level that is optimal for all operating conditions. A novel adaptive thresholding technique is presented to maximize both the receiver sensitivity and the dual-tone signal instantaneous dynamic range (IDR) for digital microwave receivers. The additional constraint placed for signal detection improves the false-alarm rate with a minimal firmware increase due to the simplicity of the proposed algorithm. Using our adaptive thresholding technique, the receiver's maximum IDR varies between 34 and 24 dB below the primary signal for primary-signal strengths between -4 and -32 dBm. Our adaptive thresholding technique was realized in firmware through two receiver designs, i.e., the initial-scaling-stage (ISS) and multistage-scaling (MSS) receiver designs. Both receiver designs show significant improvement in weak-signal spurious-free dynamic range (SFDR) performance. The MSS receiver design shows a nearly 3-dB improvement in weak-signal SFDR performance. Performance evaluations show a well-coordinated effort for adaptive thresholding system integration into the existing radar-receiver system.

This paper presents a biologically-inspired signal processor, which allows selective amplification of signals, and signal channeling mechanism to increase the contrast and sharpness of the perceived signals. The processor draws influence from lateral inhibition and integrative function mechanisms of the human nervous system. The uniqueness of the proposed design is that it combines two intelligent signal transmission mechanisms of the human nervous system with desirable capabilities: 1) wide input bandwidth, and 2) high instantaneous dynamic range. The simulations results demonstrate that the proposed design can selectively amplify weak signals among four existing strong signals and suppress noise and spurs to expose and detect weak signals, which is 58 dB below the strong ones if 4096-point FFT is used.

The complexity of timing optimization of high-performance circuits has been increasing rapidly in proportion to the shrinking CMOS device size and rising magnitude of process variations. Addressing these significant challenges, this paper presents a timing optimization algorithm for CMOS dynamic logic and a Path Oriented IN Time (POINT) optimization flow for mixed-static-dynamic CMOS logic, where a design is partitioned into static and dynamic circuits. Implemented on a 64-b adder and International Symposium on Circuits and Systems (ISCAS) benchmark circuits, the POINT optimization algorithm has shown an average improvement in delay by 38% and delay uncertainty from process variations by 35% in comparison with a state-of-the-art commercial optimization tool.

A 2.56-gigasample-per-second (GSPS) fixed-point fixed-precision dynamic kernel function fast Fourier transform (FFT) with a variable truncation scheme (VTS) is designed for real-time wideband signal detection. Using an Atmel 10-bit analog-to-digital converter (ADC), the two-tone real-time signal detection is verified for a bandwidth of 1.14 GHz with 20-MHz channelization and output throughput rates of 50 ns. The proposed design has an averaged single-signal spurious-free dynamic range (SFDR) of 27.7 dB and the ability to detect a weak input signal at -45 dBm. The overall dynamic range (DR) of the system is 40.6 dB. This is possible for a fixed-precision FFT design due to the embedded VTS to extend the total DR while preserving the instantaneous DR (IDR) relationship. In addition, with an ideal 8-bit ADC, the averaged single-signal SFDR of 32.60 dB and the two-tone signal IDR of 22 dB are achieved. The overall DR is 48.3 dB. The dynamic kernel FFT uses about 57% of the slices available on a Xilinx XC4VSX55 Virtex 4 field-programmable gate array (FPGA). In comparison with alternative implementations based on Xilinx LogicCORE 256-point IP FFT for 8-bit data, the processing time and the overall DR are considerably superior. Additional case studies that applying the windowing function and the Taylor-series-based square root approximation show favorable results utilizing the VTS for real-time data acquisition and signal-enhancement algorithms for computing high-bit-width data while minimizing the hardware.

A system-on-a-chip (SoC) built with embedded intellectual property (IP) cores offers attractive methodology design reuse, reconfigurability, and customizability. However, the integration of the design-for-testability (DfT) structures of the IP cores in these complex SoCs presents daunting challenges to designers and ultimately affects the time-to-market goals. In this paper, we introduce a design methodology to reduce the time to market by taking core test data from the design environment and automatically generating DfT structures that can easily be integrated into the SoC. A novel automated synthesis methodology to generate an SoC built-in self-test (BIST) to test the IP and custom logic cores is proposed. The proposed technique, i.e., NonExclusive Xor Test of 2D linear feedback shift register (NEXT 2D LFSR), is modeled after the principle of configurable 2D LFSR design, which generates a deterministic sequence of test vectors for random-vector-resistant faults and then random test vectors for random-vector-detectable faults. The basis of this method is to explore the design solution space for optimal 2D LFSR while embedding the test patterns by nonexclusively considering xor gates as the conventional LFSR does but including a simple logic solution for minimal hardware optimization. Moreover, the proposed approach is capable of optimizing the 2D LFSRs with consideration of the don't-care bits in the incompletely specified test patterns.

The advancement in CMOS technology with the shrinking device size towards 32 nm has allowed for placement of billions of transistor on a single microprocessor chip. Simultaneously, it reduced the logic gate delays to the order of pico seconds. However, these low delays and shrinking device sizes have presented design engineers with two major challenges: timing optimization at high frequencies, and minimizing the vulnerability from process variations. Answering these challenges, this paper presents a process variation-aware transistor sizing algorithm for dynamic CMOS logic, and a process variation-aware timing optimization flow for mixed-static-dynamic CMOS logic. Through implementation on several benchmark circuits, the proposed transistor sizing algorithm for dynamic CMOS logic has demonstrated an average performance improvement in delay by 28%, uncertainty from process variations by 32%, while sacrificing an area of 39%. Also, through implementation on benchmark circuits and a 64-b parallel binary adder, the proposed timing optimization flow for mixed-static-dynamic CMOS logic has demonstrated a performance improvement in delay by 17% and uncertainty from process variations by 13%.

This paper addresses the optimization of very large scale integration testing systems, specifically the structure design and optimization of a built-in self-test (BIST) design based on two-dimensional (2D) linear feedback shift registers (LFSRs). The 2D LFSRs can generate both precomputed test patterns (for detecting random-pattern-resistant faults) and random patterns (for detecting random-pattern-detectable faults) and have the advantages of high fault coverage and at-speed testing. To guarantee solutions, it is necessary and desirable to generate subsequences of the precomputed test patterns through the 2D LFSRs, where these subsequences retain the order of the test patterns, particularly for testing sequential circuits. For the design and optimization of the 2D LFSRs, the following two problems need to be solved: 1) the good partitioning of the precomputed test patterns into disjoint subsequences in order to achieve a minimal hardware and 2) the structure design and optimization of the 2D LFSRs to generate the test patterns in each partitioned subsequence. The optimization of the 2D LFSRs is modeled as an integer program (a logic optimization model) that determines the coefficients of the recursive Boolean equations that govern the generation of the test patterns. For a sequence of the test patterns, this model finds the minimal-hardware implementation of the 2D LFSRs. This logic optimization model can be applied to both test-per-scan (serial BIST) and test-per-clock (parallel BIST). This paper presents how this model is embedded in a heuristic framework to partition the test patterns into subsequences from the configurable 2D LFSRs. The testing hardware is small as the configurable architecture allows the tester to incrementally generate the precomputed test patterns by modification to the feedback of the 2D LFSRs. Results of benchmark circuits show that significant hardware reduction and higher fault coverage are achieved. The resulting multisequence test generator is a regular structure and is easy to implement. The logic optimization model is applicable to both completely and partially specified test patterns and can be adopted for other LFSR-based structure design and optimization.

This paper presents a 4-b low-power, low-voltage flash analog-to-digital converter (ADC). The proposed ADC is pipelined and mainly consists of three stages: 1) track-and-hold (T/H); 2)differential comparator; and 3) differential cascode voltage switch with pass gates (DCVSPG) encoder. The T/H uses a current-mode dual-array structure to reduce the aperture jitter for high-input signal frequency. The differential comparator eliminates the use of the resistor ladder circuit by generating the reference voltages internally. The DCVSPG encoder has a full output signal swing and compact logic design style of pass gate circuits, which makes it suitable for high sampling frequency. The DCVSPG encoder reduces the power consumption by a factor of 88% as compared with the conventional ROM encoder. The ADC is designed in 130-nm CMOS technology. Fast Fourier transform tests prove proper operation of the ADC sampled at 2.5 GHz for the input signal frequency up to 1 GHz

A wide tuning band pass filter (BPF) with steep roll-off high rejection and low noise figure is presented. The design feature of steep roll-off high stopband rejection (>20 dB) and low noise figure (

Today's very deep submicron IC technology enables high-performance analog and digital applications to be integrated on a single piece of silicon. For this effort, a design of 2.5 giga-sample per second (GSPS) receiver-on-a-chip (ROC) is presented. For our design, we take advantage of a compensation technique to reduce spurs and improve instantaneous dynamic range. A major goal is to produce a low-cost, small, and lightweight, and low-power ROC. Our design will cover a 1-GHz bandwidth (125 - 1125 MHz), and it will correctly process two simultaneous signals by detecting their frequency, pulsewidth (PW), and time of arrival (TOA). The single or dual signal, spur-free dynamic ranges and two signal instantaneous dynamic ranges of our design are high. The minimum frequency separation of two signals is 10 MHz (one channel width), and the maximum amplitude separation (dynamic range) of two signals is 18 dB with the second signal false alarm less than 1%.

A configurable two-dimensional (2-D) LFSR based test generator and an automated synthesis procedure are presented. Without storage of test patterns, a 2-D LFSR based test pattern generator can generate a sequence of precomputed test patterns (detecting random-pattern-resistant faults) and followed by random patterns (detecting random-pattern-detectable faults). The hardware overhead is decreased considerably through configuration. The configurable 2-D LFSR test generator can be adopted in two basic BIST execution options: test-per-clock (parallel BIST) and test-per-scan (serial BIST). Experimental results of test-per-clock and test-per-scan BIST of benchmark circuits demonstrate the effectiveness of the proposed technique. The configurable 2-D LSFR can also be adopted in chip-level and system-on-a-chip (SoC) BIST.

A complete behavioral fault simulation and automatic test pattern generation (ATPG) system for circuits modeled in VHDL has been presented in this research. Ten different behavioral fault models were selected and used to generate test patterns through fault simulation. One major advantage of the current system is that full VHDL (IEEE-STD 1076) constructs can be handled because fault simulation are performed by comparing the simulation results of good and faulty models utilizing a VHDL simulator. Areas of future research include the refinement of existing fault models, defining new behavioral fault models to reduce the gap between the behavioral fault models and gate-level failures, and the development of a better test pattern generator for target faults. Another valuable enhancement would be to run fault simulation in parallel, by embedding multiple faulty models into one test bench to simulate many faults concurrently. This would speed up the behavioral fault simulation in an efficient way. Gate-level fault simulation is not an effective solution for complex microcircuits. The results of this research show that behavioral fault simulation will remain as a highly attractive alternative for the future generation of VLSI and system-on-chips (SoC).

Carry lookahead adders have been, over the years, implemented in complex arithmetic units due to their regular structure which leads to efficient VLSI implementation for fast adders. In this paper, timing-driven testability synthesis is first performed on a tree adder. It is shown that the structure of the tree adder provides for a high fanout with an imbalanced tree structure, which likely contributes to a racing effect and increases the delay of the circuit. The timing optimization is then realized by reducing the maximum fanout of the adder and by balancing the tree circuit. For a 56-b testable tree adder, the optimization produces a 6.37%increase in speed of the critical path while only contributing a 2.16% area overhead. The full testability of the circuit is achieved in the optimized adder design.

As a modern radar receiver must rapidly search a large frequency range with maximum sensitivity, capabilities such as high instantaneous dynamic range (IDR), good multiple-signal-detection capability, wider bandwidth (BW), and high-frequency resolution are indispensable. Many techniques proposed to improve digital wideband receiver performance are computationally intensive and limit their real-time performance due to hardware constraint. In this paper, an innovative three gigasample-per-second hybrid computing platform digital wideband receiver system is presented, which employs two Nvidia Tesla C2050 graphics processor units and a Xilinx Virtex-5 field-programmable gate array for hardware acceleration to drastically improve receiver performance over its predecessor designs. The receiver detects five simultaneous signals in 1.25-GHz BW (125-1375 MHz) with a maximum IDR of 42.5 dB and a frequency resolution of 0.5 MHz. The proposed receiver architecture achieves high-resolution spectral estimation and employs a hardware mechanism for multiple-signal detection before the next set of data arrives for processing.

Recently a multiple-sequence test generator was presented based on two-dimensional linear feedback shift registers (2-D LFSR). This generator can generate a set of precomputed test vectors obtained by an ATPG tool for detecting random-pattern-resistant faults and particular hard-to-detect faults. In addition, it can generate better random patterns than a conventional LFSR. In this paper we describe an optimized BIST scheme which has a configurable 2-D LFSR structure. Starting from a set of stuck-at faults and a corresponding set of test vectors detecting these faults, the corresponding test pattern generator is determined automatically. A synthesis procedure of designing this test generator is presented. Experimental results show that the hardware overhead is considerably reduced compared with 2-D LFSR generators.

Due to the increasing level of integration achieved by Very Large Scale Integrated (VLSI) technology, traditional gate-level fault simulation is becoming more complex, difficult, and costly. Furthermore, circuit designs are increasingly being developed through the use of powerful VLSI computer-aided design (CAD) synthesis tools which emphasize circuit descriptions using high-level representations of functional behavior, rather than physical architectures and layout. Behavior fault simulation applied to the top functional level models described using a hardware description language offers a very attractive alternative to these problems. A new way to simulate the behavioral fault models using the hardware description language (HDL), such as VHDL, is presented. Tests were generated by carrying out the behavioral fault simulation for a few circuit models. For comparison, a gate-level fault simulation on the equivalent circuit, produced via a synthesis tool, was used. The performance analysis shows that a very small number of test patterns generated by the behavioral automatic test pattern generation (ATPG)/fault simulation system detected around 98 percent of the testable gate-level faults that were detected by random test.

This work introduces a built-in self-test (BIST) design methodology that can sequentially test large very large scale integrated (VLSI) circuits with very high fault coverage. The proposed techniques, circular BIST ((BIST) and (BIST with pseudopartial scan (PPSCAN), are modeled after the principles of the circular self-test path (CSTP). The basis of this method is to trade a minimal increase in hardware overhead for a large increase in fault coverage. It is shown that this technique yields a much higher fault coverage with reasonable time and test vector length when compared with existing sequential test methods. The effectiveness of the technique has been demonstrated by applying it to practical VLSI circuits, which include: 1) the system control coprocessor (CP0) of MIPS 3000 central processing unit (CPU) core and 2) the SIMD graphic engine, namely, enhanced memory chip (EMC). The BIST results show that (BIST and its derivative (BIST with pseudopartial scan (PPSCAN) are feasible for practical VLSI designs and generate BIST with high fault coverage and low overhead.

Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. A paper by Lowy (1996) is quite interesting in this regard. The author talks of a parallel architecture of linear feedback shift registers (LFSRs) and sequence generators that have a lower power dissipation than that of conventional LFSRs. This paper comments on some design improvements and explores some techniques that would make the LFSRs capable of handling different low-power applications. The advantages of using nonprimitive polynomials with two taps in implementing low-power LFSRs are analyzed in this paper. It is found that if the taps are taken from the last and center of the flip-flops, the number of switch requirements reduces from the order of M+N to the order of N, where N is the length of the shift register and M is the number of taps. This sort of tapping also results in a simpler switch minimization algorithm. With our strategies, it is possible to generate much better sequences from Lowy's LFSRs structure. Moreover, power dissipation is constant in our case, independent of the number of stages in the LFSRs. Our simulations show that the percentage of power improvement to conventional serial LFSRs is from 51.65% (N=18) to 68.51% (N=28).

For pt. I see ibid., vol. 32, no. 1, p. 1-15 (1996). Common buses are an extremely efficient structure for achieving area minimization so that the bus-oriented interconnection of registers and data operators plays an important role in data path synthesis. The overriding design goal is efficiently allocating the minimum number of buses and gating elements (i.e. multiplexers) for achieving communication between the data path elements. New efficient algorithms for the automated allocation of buses in data paths have been developed. The entire allocation process can be formulated as a graph partitioning problem. This formulation readily lends itself to the use of a varieties of heuristics for solving the allocation problem We present efficient algorithms which provide excellent solutions to this formulation of the allocation problem The operation of the algorithms is clearly demonstrated using detailed examples.

A data path consists of memory elements (i.e., registers), data operators (i.e. ALUs) and interconnection units (i.e. buses) to control the data transfers in the digital system. Many approaches to hardware allocation for data path synthesis have been proposed in the literature; however, only single-port memory is considered for register allocation and no efficient synthesis approach for multiport memory synthesis. A novel design methodology for data path synthesis using multiport memories is proposed which can be applied to hardware allocation algorithms or to already synthesized data path as a postprocessor to achieve a better design. Illustrations of applying this method to different synthesis examples are presented. Results and improvements over previous techniques are demonstrated. Experiments on benchmarks show very promising results.

New, efficient algorithms for the automated synthesis of buses in data path design are presented. Modifications to the technique of Generalized Clique Partitioning (GCP) are discussed which lead to better designs and reduced computation time in large synthesis problems. The new approach, Weighted Cluster Partitioning (WCP), eliminates the need for backtracking. The algorithm guides the process of bus formation by assigning a higher weight to those interconnection units that should be combined first. The operation of the WCP algorithm is clearly demonstrated using a detailed example.A modified priority ordering in the selection of the candidate pair is also discussed which can improve the performance of GCP and WCP. We demonstrate that GCP II performs better than GCP, while WCP II consistently produces the best results of all these algorithms on a set of large synthesis examples.

The goal of task allocation in a set of interconnected processors (computers) is to maximize the efficient use of resources and thus reduce the job turnaround time. Proposed is a simple yet effective method to allocate the tasks in multicomputer systems for minimizing the interprocessor communication cost subject to resource limitations defined by the system and designer. The limitations can be viewed as results from the load balancing since the execution time of each task, the number of available processors, processor speed, and memory capacity are known to the system or designer. As the number of processors increases, the probability of a failure existing somewhere in the systems at any time also increases. Very few established task allocation models have considered the reliability property. In multicomputer systems, we define system reliability as the probability that the system can run the tasks successfully. After the (nonredundant) task scheduling strategy is defined, tasks are then reallocated to processors statically and redundantly. This is a form of time redundancy, in which if some processors fail during the execution, all tasks can be completed on the remaining processors (but at a longer time). Due to static preallocation of tasks this method is simpler and thus more practical than well-known dynamic reconfiguration and rollback recovery techniques in multicomputer systems. We demonstrate the effectiveness of the task allocation and reallocation for hardware fault tolerance by illustrations of applying the methods to different examples and practical communications network multiprocessor system. >

A simple yet effective method for improving multicomputer multiprocessor system reliability via redundant allocation of tasks to computers (processors) is described. Given any known (nonredundant) scheduling strategy, tasks are allocated to processors statically and redundantly using a k-circular shifting (KCS) algorithm. so that if some processors fail during the execution. all tasks can be completed on the remaining processors (but at a longer time). Redundant allocation of independent tasks to identical processors (computers), subject to real-time constraints on total execution time, is discussed in detail, and analytic reliability estimates are derived. The longest processing time scheduling is given as an example of nonredundant deterministic scheduling of independent tasks. Processor utilization for redundant task-allocation is discussed and compared with standby redundancy: the authors' KCS algorithm achieves much higher processor utilization than standby redundancy. >

Synthesis for testability ensures that the synthesized circuit is testable by exploring the fundamental relationship between don't care and redundancy. With the exploration of the relationship, redundancy removal can be applied to improve the testability, reduce the area and improve the speed of a synthesized circuit. The test generation problems have been adequately solved, therefore an innovative testability synthesis strategy is necessary for achieving the maximum fault coverage and area reduction for maximum speed. This paper presents a testability synthesis methodology applicable to a top–down design method based on the identification and removal of redundant faults. Emphasis has been placed on the testability synthesis of a high-speed binary jumping carry adder. A synthesized 32-bit testable adder implemented by a 1.2 μm CMOS technology performs addition in 4.09 ns. Comparing with the original synthesized circuit, redundancy removal yields a 100% testable design with a 15% improvement in speed and a 25% reduction in area.

Many IC design houses failed to be market leaders because they miss the market window due to timing closure problems. Compared to half-micron designs, the amount of time spent on timing verification has greatly increased. Cell delays can be accurately estimated during logic synthesis. However, interconnect delays are unknown until the wire geometry is defined in physical design. Logic synthesis using the cell library models for interconnect delay estimates may be statistically accurate, but can not predict the delay of individual nets accurately. Delay estimates for individual nets (global nets, long wires, large fan-outs, buses), which matter most for the critical paths can be inaccurate and cause a design failure. Inaccurate timing verification causes silicon failure in shipped products that results in the loss of millions of dollars spent designing a high-performance product and potentially larger costs due to lost market share. Full-chip, sign-off verification with silicon-accuracy will allow these problems to be discovered and fixed before tape-out.

A data path consists of memory elements (i.e. registers), data operators (i.e. ALUs) and interconnection units (i.e. buses) to control the data transfers in the digital system. Many approaches to memory synthesis have been proposed in the literature. However, only single port memory is considered for register allocation and no efficient synthesis approach for multiport memory synthesis. In this paper, an efficient method, Partitioned Dependence Matrix (PDM), is presented for memory synthesis which deals not only with single port memory synthesis but also multiport memory synthesis according to the design constraints. With suitable modifications, the proposed technique can also be applied to multiport memory synthesis in which the maximum number of read ports is different from the maximum number of write ports. Therefore, the entire design space is explored and has the capability to handle early architectural design exploration so that the quality of designs produced by an automatic synthesis tool is more adequate for production use in comparison to manual design. Illustrations of applying this method to different synthesis examples are presented. Results and improvements over previous techniques are demonstrated. A key element in our approach is the successful adoption of techniques originally developed for problems in test generation to the field of memory synthesis.

Timing analysis and optimization is one of the key areas in modern VLSI design and has become bottleneck in designing multi-million gate systems. Consequently, computer-aided design research in this area has shown in a new renaissance after the advent of deep sub-micron IC technology and the accompanying restrictive performance constraints. Effects related to interconnect dominance has resulted in technical problems in areas such as floorplanning, placement, routing and performance prediction, and therefore has made accurate and effective timing analysis and optimization more challenging. The current special issue of VLSI DESIGN Journal is devoted to papers that provide high-quality ideas and results in critical areas related to the timing analysis and optimization for deep sub-micron IC. The first paper called, “Timing Challenges for Very Deep Sub-Micron (VDSM) IC” is by Lin et al. The paper presents current and future timing challenges for VDSM IC. It presents why traditional design flow failed in timing sign-off and how silicon-accurate timing tools are necessary to overcome timing challenges and limitations that cause timing convergence and capacity problems in VDSM IC technology. The second paper is by Dhaou et al. Its title is “Energy Efficient Signaling in DSM Technology.” The key idea is to combat crosstalk noise and to reduce the power consumption while driving the global wire at an optimal delay by reducing voltage swing with buffer insertion and resizing. In 0.25mm CMOS, over 60% of energy-saving can be achieved if supply voltage is reduced from 2.5 down to 1.5 V. The third paper is written by Chen et al., entitled “Simultaneous Buffer-Sizing and Wire-Sizing for Clock Tress Based on Lagrangian Relaxation.” In this paper, a Lagrangian relaxation algorithm for simultaneously optimizing delay, power, skew, area, and sensitivity in clock tree is presented. The effectiveness and accuracy of algorithm is demonstrated. The fourth paper is by Hu et al. Its title is “Performance Driven Global Routing Through Gradual Refinement.” The authors present a heuristic for interconnect global routing that can optimize routing congestion, delay and the number of bends that are oftenly competing objectives. In addition to exploiting timing constrained routing flexibility, a gradual refinement method is applied for simultaneous optimization on congestion, timing and the number of bends. Experiments on benchmarks confirm the effectiveness of this method. The fifth paper is written by Arunachalam et al and is entitled “Accurate Coupling-Centric Timing Analysis Incorporating Temporal and Functional Isolation.” This paper presents a timing analysis methodology TACO that can accurately bind the arrival times in the presence of coupling. The timing windows at the aggressor can be used to determine whether the aggressor can switch in conjunction with the victim. Results of industrial examples show that the proposed method actually helps in reducing pessimism in the timing analysis. The sixth paper is authored by Lee et al. and is entitled “CMOS Delay and Power Model Equations for Simultaneous Transistor and Interconnect Wire Analysis and Optimization.” Generalized delay and power equations are proposed in this paper for CMOS circuit optimization achieved by transistor and interconnect minimization. The equations help analyze the entire power-delay trade-off with less complexity and fast computation time. The seventh paper is written by Huang and is entitled “Improving the Timing of Extended Finite State Machines via Catalyst.” In this paper, a timing optimization technique for a complex finite state machine that consists of random logic and data operator is presented. The proposed technique based on the concept of catalyst adds a functionally redundant block to the original circuit so the timing critical paths are divided for speed improvement. The eighth paper is by Huang et al. Its title is “TimingDriven-Testable Convergent Tree Adders.” The tree structure of adders is normally unbalanced and therefore generates high fanout in timing critical paths that may cause racing and increase the delay. A timing optimization