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Satellites that orbit planets with radiation belts are subjected to experience internal electrostatic discharge (IESD) events as they interact with charged particles. When charge accumulation exceeds the threshold of the dielectric material on the spacecraft, large discharges occur. The discharges generate electromagnetic pulses that couple to the antennas and induce high voltages. Protection from these discharges is of paramount concern for instrument fidelity of the spacecraft. Modeling the spacecraft and simulating these IESD events using a Maxwell's equations solver can describe how IESDs couple to the antennas of the spacecraft and thus provide information on how to properly protect the instruments from these high voltages. In particular, the finite-difference time-domain (FDTD) method offers advantages for this application over other electromagnetic numerical solvers because in a straight-forward manner it can simulate wideband transient pulses and also accurately solve near-field effects. A generalized analysis method is proposed and carried out in which an FDTD model is used to obtain transfer functions for IESD's occurring at hundreds of different locations on the spacecraft, which are then linearly combined to represent a wide variety of possible scenarios.

This paper reports investigation of failure mechanisms of GaN-on-Si power device under electrostatic discharge (ESD) stress using on-wafer transmission-line pulse (TLP) testing. Hot-hole injections under the gate and filament formation in the buffer layer are examined by monitoring the threshold voltage (Vth) and on-resistance (Ron) subjected to a floating gate or an off-state gate voltage. Distinct and continued degradation has been observed after the ESD stress is removed indicating a slow de-trapping process due to deep-level buffer traps. Finally, 2D device simulation is used to probe the physical insight into failure mechanisms.

Electrostatic discharge (ESD) failures in high-speed integrated circuits (ICs) cause critical reliability problems in electronic devices. Transient voltage suppressor (TVS) diodes are installed on high-speed I/O traces to improve system-level ESD protection. To protect the circuit, the majority of ESD current must flow into the external TVS diode rather than into the IC, but due to turn- on behavior, the TVS diode may not snap back when needed and the IC's internal protection may take most of the current. These race conditions between the internal and external ESD protection circuits were investigated for a universal serial bus(USB) interface board. The transient turn- on behavior of the on-chip and off-chip protection circuitry was characterized by measurements and by system efficient ESD design (SEED) simulations. The effect of transmission line pulses (TLP pulses) and power supply voltages of different sizes on the response of the protection circuitry were monitored and compared with SEED simulations. SEED models showed good agreement with measurements and were used to study the impact of passive components added to a high-speed trace or within the IC package on the ESD protection response. Results show the importance of properly accounting for the parasitic resistance and inductance between the on-chip diode and off-chip TVS diode, as well as the length of the transmission line when choosing the external TVS device. Results also show that testing must be performed using mid-level events to account for possible problems due to race conditions.

To enable accurate system-level electrostatic discharge (ESD) simulation, this article applies statistical learning to obtain I/O port models of the victim integrated circuits (ICs). A quasi-static I–V model derived using kernel regression can capture the circuit board dependency of the behavior observed at the I/O pin, regardless if there is snapback. The non-parametric kernel model can be reduced to a system-specific parametric model, which has smaller requirements for computing time and memory. In some cases, transient system-level ESD simulation may require the IC model to replicate the dynamic behavior of the nonlinear circuit. A recurrent neural network is demonstrated to be a suitable model in such cases. This article provides a detailed RNN training flow for IC pin modeling, and presents a Verilog-A implementation of the RNN for use with Simulation Program with Integrated Circuit Emphasis (SPICE)-type simulators.

This letter focused on the additive effect of horizontal Schottky diodes on the drain side of a high-voltage p-channel laterally diffused metal–oxide–semiconductor (pLDMOS). These components were evaluated using transmission-line pulse and human body model (HBM) tests. When the parasitic Schottky area at the drain was smaller, the Schottky characteristics were less obvious; the device’s current mostly flowed through the heavily doped $\text{P}^{+}$ area, and the improvement in ${I}_{\text {t2}}$ was minor. When the parasitic Schottky area covered more than 60% of the drain side, the Schottky area accounted for the majority of current flow; therefore, the electrostatic discharge current could flow more evenly. These modified pLDMOSs can withstand higher voltages because of their parasitic Schottky diodes and higher impedance. In addition, their ${I}_{\text {t2}}$ values are superior to those of normal pLDMOSs. With the drain side of the pLDMOS completely covered by Schottky diodes, the device produced the highest ${I}_{\text {t2}}$ value of 1.659 A (130.4% higher than that of the reference sample), an HBM value of 5 kV (300% higher than the reference), and an improved holding voltage (4% greater than that of the reference).

A dual-MOS-triggered silicon-controlled rectifier (DMTSCR) has been firstly developed for high-voltage (HV) electrostatic discharge (ESD) protection. Compared to the reported SCRs with modified structures, the DMTSCR harvests a series of advantages such as a high holding voltage ( $V_{h}$ ), a strong ESD robustness, and a low $V_{t1}$ , thanks to its embedded structures including a gate-to-VDD PMOS, a gate-grounded NMOS, and a modified SCR. Thus, the DMTSCR has the largest figure of merit as high as 1.8 mA/ $\mu \text{m}^{2}$ . By further optimizing the layout and the key spacing between the embedded PMOS and NMOS of DMTSCR, $V_{h}$ increased from 8.4 to 17.4 V, the turn-on resistance remarkably decreased to $0.4~\Omega $ , and the turn-on voltage was clamped at $V_{h}$ . The optimized DMTSCR with a small chip area possesses an ESD robustness of 3000 V evaluated by the human body model. Meanwhile, the operation mechanism simulated by Sentaurus exhibited good agreements with the theoretical circuit analysis, and the simulated electrical characteristics were consistent with those measured from the experimental devices. The layout-optimized DMTSCR with good clamping ability and zero snapback voltage is a promising solution for stacking to meet various HV ESD protection requirements.

On-chip electrostatic discharge (ESD) protection is becoming more challenging for integrated circuits (ICs) made in advanced technology nodes. The ESD-induced design overhead, including ESD parasitic effects and layout area, inherent to the traditional in-Silicon PN-junction-based ESD protection devices, rapidly becomes unbearable to high-performance and complex ICs. A disruptive above-Si mechanical ESD switch device, made in CMOS backend using a graphene nano-electromechanical-system (gNEMS) structure, was recently devised and demonstrated using poly-crystalline graphene films. This paper reports design, fabrication and comprehensive characterization of single-crystalline gNEMS ESD switch devices. Measurement using transmission line pulse (TLP) and very fast transmission line pulse (VFTLP) ESD testing reveals superior ESD protection capability of gNEMS devices made in single-crystalline graphene over its poly-crystalline counterparts, achieving a record-high ESD current handling capability of ${\text{I}}_{t2} {\sim }1.19 {\times }10^{10}\text{A}$ /cm2 under TLP zapping and ${\text{I}}_{t2} {\sim }6.09{\times }10^{9}\text{A}$ /cm2 under VFTLP stressing. The ESD robustness enhancement related to single-crystalline graphene material property is discussed.

This article proposes a novel power p-GaN high-electron-mobility transistor (HEMT) with self-triggered discharging channel to improve gate-to-source electrostatic discharge (ESD) robustness. The self-triggered discharging channel consists of a small-size self-triggered p-GaN HEMT, a current-limiting resistor ${R}_{{1}}$ , and a proportional amplification resistor ${R}_{{2}}$ . At ESD events, the proposed power p-GaN HEMT will be self-triggered by the high transient ESD voltage, and hence the accumulated electrostatic charges at its gate will be released through the self-triggered discharging channel. This avoids the gate-to-source damage of the proposed device, thereby enhancing the gate-to-source ESD robustness. Compared with the conventional power p-GaN HEMT, simulation results show that the transmission line pulsing (TLP) current handling capability (over 6.5 kV human body model failure voltage) of the proposed device is improved by 1900% without compromising other device characteristics. In addition, the fabrication process of the proposed device is fully compatible with the traditional power p-GaN HEMT platform, and the increase of total active area is less than 0.5%. The proposed device with self-triggered discharging channel can be a good reference for the design of power p-GaN HEMT with high ESD robustness.

Current filament (CF)-related double-hysteresis ${I}$ – ${V}$ behavior and holding current, ${I} _{\text {HOLD}}$ , are analyzed using experiments and 3-D technology computer-aided design (TCAD) simulation in silicon-controlled rectifiers (SCR) for system-level electrostatic discharge (ESD) protection. Our 3-D TCAD methodology uses up and down quasi-dc current sweeps to reveal a memory effect in the current density distribution along the device width. ${I} _{\text {HOLD}}$ is related to the smallest possible CF where the self-sustaining SCR action takes place during down current sweep. ${I} _{\text {HOLD}}$ exhibits a nontrivial dependence on device width, depending on whether a CF is created or not. Analyzing devices of different layouts shows that ${I} _{\text {HOLD}}$ values determined from experiments and 3-D TCAD are almost layout-independent and substantially lower than those evaluated from 2-D TCAD. ${I} _{\text {HOLD}}$ calculated by 3-D TCAD in edge-terminated devices is higher than that in 3-D structures obtained from simple width-extended 2-D doping profiles. The use of latter devices, thus, simplifies the 3-D TCAD ${I}$ – ${V}$ analysis and provides a safe margin for ${I} _{\text {HOLD}}$ prediction. The work is relevant for designing the latch-up immunity of ESD protection devices, and it also shows that conventional 2-D TCAD can provide unwanted overestimation of ${I} _{\text {HOLD}}$ .

A unique failure mechanism for International Electrotechnical Commission (IEC) stress through a common-mode (CM) choke is investigated. The presence of a CM choke in the stress path was found to change the current waveform shape that the electrostatic discharge (ESD) protection device experiences on-chip. Minor variations in the stress current waveform shape for specific IEC stress levels are found to cause an unexpected window failure in drain-extended nMOS silicon controlled rectifier (DeNMOS-SCR). The 3-D technology computer-aided (TCAD) simulations are used to understand the device behavior and failure under the peculiar two-pulse-shaped IEC current waveform attributed to the presence of a CM choke. DeNMOS-SCR failure sensitivity to different components of the unique pulse shape is studied in detail. A novel device architecture is proposed to increase the DeNMOS-SCR robustness against the peculiar two pulse stimuli. The proposed DeNMOS-SCR was found to eliminate the window failures against system-level IEC stress through a CM choke in communication pins in automotive ICs. The proposed concept is universal and can be extended to all high-voltage DeNMOS-SCRs. A detailed physical insight is provided for the operation of the engineered structure.

In this paper, the electrostatic discharge of solar arrays in spacecraft energy systems is taken as the research object. The influence and internal mechanism of external electromagnetic radiation on electrostatic discharge is studied. Meanwhile, the charging and discharging test platform of spacecraft solar arrays under a strong field is first established. Then, the influence of irradiation field strength, electron beam energy and beam density on electrostatic discharge of solar arrays is analyzed and summarized. The results show that during the irradiation process of solar arrays using a high-energy electron beam under vacuum conditions, the higher the electron beam energy and the beam current density, the higher the discharge frequency of the solar array. When the intensity of the external electromagnetic radiation field increases, the discharge frequency also increases. Under the action of external radiation field with the same peak field strength, the larger the gap, the smaller the discharge frequency. With the increase in the field strength, the potential difference of each part of the solar array becomes smaller, and the peak of the discharge current decreases. The research results can provide technical reference for electrostatic protection of spacecraft solar arrays.

This letter presents a fully integrated wideband, ultralow average noise figure (NF), low power consumption, compact, and electrostatic discharge protected 6.7–15.3-GHz low-noise amplifier (LNA). A peak-gain distribution technique with a large transistor and two-stage broadband noise matching technique are proposed. For verification, a two-stage common source LNA is implemented in a 65-nm bulk complementary metal–oxide–semiconductor technology. The fabricated LNA achieved an average NF of 2.08 dB and an average gain of 19.1 dB with in-band gain ripple of ±0.75 dB in the frequency range of 7.6–14.7 GHz. It has a 3-dB fractional bandwidth of 78% and the third-order input intercept point is −9.0 dBm at 10 GHz. It consumes a 16 mA at a 0.8-V supply and has an area of 0.144 mm2.

System efficient electrostatic discharge (ESD) design is an effective method for simulating the ESD behaviors of a system. Based on this simulation method, this article mainly investigates the transient behaviors of a system-level ESD protection circuit with and without a 2.5 V power supply. During power- on state, latch-up levels of a feedback power clamp protected by off-chip elements are predicted and mainly analyzed under machine model stress. During power- off state, the physical failure of a hybrid-triggered power clamp under surge stress is investigated. In addition to the utilization of transmission line pulsing (TLP) I-V curves, transient TLP waveforms are also used for building the component models in the system-level ESD protection circuit. Moreover, the relevant measurements for the power- on state and power- off state are included in this article for verifying the simulation results. For ESD designers, this article provides a complete modeling and analysis process of co-design protection circuit to investigate the electrical behaviors.

Circuits design that meets various IEC electrical overstress (EOS) standards is still a challenge, for that different kinds of EOS are at different frequency bands. In this paper, a physics-based transient simulation and modeling method is proposed, which can simulate wide-frequency EOS including electrostatic discharge (ESD) and AC characteristics. In this method, the physical model is used to characterize the nonlinear semiconductor devices in the finite-difference time-domain (FDTD)-SPICE co-simulation. Moreover, the modeling and physical parameters extraction method of the ESD protect devices, the transient voltage suppressor diode, is demonstrated. Taking an EOS protection circuit for example, it is modeled and simulated by the proposed method. Moreover, the circuit is also simulated by the widely-used System-Efficient ESD Design (SEED) method, in which the TVS diode is modeled based on 100 ns Transmission Line Pulse (TLP) measurements. The experiments show that both this method and SEED method can characterize the IEC system-level ESD behaviors well. However, the error of the SEED is about 219.2% at 10 MHz AC characteristics, but the maximum error of the proposed method is only 7.8%. Hence, compared with the widely-used SEED method, this method is more accurate when characterizing the EOS event during AC operation and switching.

An electrostatic discharge (ESD)-protected one-time-programmable (OTP) memory front-end circuit, for high-voltage (HV) applications, designed and manufactured in silicon-on-insulator (SOI) technology, is presented. The SOI technology meets HV functional-isolation and level-shifting requirements but is not suitable for advanced analog circuits. The presented OTP memory is discussed as an introduction to digital programmability in the considered technology. The memory element consists of an antifuse type structure and is implemented using a 5-V nMOS with $\text {L}={1}\,\, \mathbf {\mu \text {m}}$ and $\text {W}={1.2}\,\, \mathbf {\mu \text {m}}$ . The cell memory allows for significant area and power savings in the adopted HV technology. Conditions for this require that an efficient ESD protection will guarantee safe operation, even in the presence of a small and fragile on-chip element whose undesired burning would compromise the programming mechanism, and consequently the reliability, of the circuit. Details about the circuit design implementation of the front-end circuit for both read and write circuits and ESD protection are described with experimental results validating the proposed implementation.

A novel electrostatic discharge (ESD) protection device based on an n-type metal–oxide–semiconductor field-effect transistor (NMOSFET) with segmented topology was proposed and investigated, considering the material characteristics of 4H-SiC, which is a wide-bandgap material (3.3 eV). ESD phenomena are important in terms of semiconductor reliability, and the benefits of using 4H-SiC as a material can provide robustness and excellent thermal reliability to ESD protection devices. The proposed device improves the wide range of snapback phenomena caused by the high critical electric field (2.4 MV/cm), in comparison to using Si (0.25 MV/cm); it also improves triggering characteristics and provides a high holding voltage. The proposed device and a traditional silicon-controlled rectifier, a gate-grounded-NMOS, and a gate-body floating NMOS were fabricated using the 4H-SiC process. The electrical characteristics of the experimental devices, determined by a transmission-line-pulsing system, were comparatively analyzed. Additionally, this article presents the analysis of the optimization of electrical characteristics according to the critical design variables of the proposed device, stacking for high-voltage applications, and reliability test results for high temperatures (300–500 K).

Electrostatic discharge (ESD) can cause digital industrial equipment (DINE) to malfunction or even break down. To assess the impact of ESD, it is important to know the statistical characteristics of the current and voltage parameters on the body of equipment being tested. An installation that allows attaining these parameters is proposed. The experimental current and voltage parameters of ESD are measured at various capacitances of the DINE body and various ground resistances at voltages from 2 to 25 kV. The results of measuring the voltage increment rate, the maximal and the average rate of voltage change, and the rate of current change in an air ESD can be used to forecast the effect of ESD on equipment.

Transient voltage suppressor (TVS) has been widely used on the printed circuit board (PCB) to protect the microelectronics system against the system-level electrostatic discharge (ESD) and electrical fast transient/burst (EFT/B) events. However, the signal integrity of the system operations may be destroyed after the system-level ESD and EFT/B immunity test, if the TVS were designed with a holding voltage of lower than the operating voltage of the CMOS ICs equipped in the system. In this work, the signal integrity of microelectronics system protected by the TVS with different holding voltages was studied under the system-level ESD and EFT/B immunity test. By monitoring the transient voltage waveforms in the time domain during system-level ESD and EFT/B immunity test, the system malfunction has been found when the TVS is with a lower holding voltage. Therefore, the holding voltage of the TVS must be greater than the system operating voltage to maintain the signal integrity in the field applications.

In the emerging age of the Internet of Things (IoT), energy-efficient and reliable connection among sensor nodes gain prime importance. Wireless engineers encounter a trade-off between sensors energy requirement and their reliable full connectivity. Consequently, the need to find the optimal solution draws the attention of many researchers. In this paper, the Electrostatic Discharge Algorithm (ESDA) is proposed, implemented, and applied to minimize energy needs of a sensor node while ensuring the fully-connectedness of each node. The obtained results show that the proposed method achieves better results than those found in the literature using the particle swarm optimization method in terms of energy savings and reliable connectivity.

Integrated circuit (IC) and printed circuit board (PCB) electromagnetic (EM) modeling methods are becoming essential during the development of automotive electronic control units. Academic and industrial efforts focus on radiated and conducted emissions caused by flaws in PCB design from EM compatibility (EMC)/electrostatic discharge (ESD) point of view, including improper placement, grounding, and shielding of ICs. In this article, the effectiveness of noise suppressing sheet material for the mitigation of radiated emission at global positioning system (GPS) and Global'naya Navigatsionnaya Sputnikovaya Sistema (GLONASS) bands according to U.S. automotive original equipment manufacturer (OEM) requirements is investigated. A few test scenarios that include the NSS material are explored to gauge its performance in near-, intermediate-, and far-field regions, using 3-D full-wave numerical simulations and EMC laboratory experiments.

In this article, electrostatic discharge (ESD) induced soft failures (SFs) of a USB3 Gen1 device are investigated by direct transmission line pulse injection with varying pulsewidth, amplitude, and polarity to characterize the failure behavior of the interface and to create a SPICE model of the voltage and current waveform dependent failure thresholds. ESD protection by transient-voltage-suppression diodes is numerically simulated in several configurations. The results show viability of using well-established hard failure mitigation techniques for improving SF robustness. A good agreement between numerical simulation for optimized board design and measurements are achieved. A novel concept of SF system efficient ESD design is proposed and demonstrated to be effective for making decisions during early product development, in board designing and prototyping phase.

This article investigates the effects of different gate coupling voltage and gate voltage duration on electro-static discharge (ESD) performance of several NMOS-based power rail protection devices. Through simulation and transmission line pulse (TLP) test, it is found that there are two modes in the conduction process of the main clamping NMOS: channel conduction state and parasitic NPN conduction state. Different gate voltage and duration bring the two conduction states different proportions in the whole working process, which give the device very different robustness. The results show that under the condition of small gate voltage and long duration and the condition of large gate voltage and short duration, the device can achieve optimal performance because the trigger voltage can be reduced, and the parasitic NPN can be turned on in time to release most of the current.

In advanced charged device model (CDM) protection engineering, it is necessary to provide dedicated dual-directional electrostatic discharge (ESD) protection between input/output (I/O) and ground (GND) to discharge the large amount of charge stored in the silicon substrate efficiently. This letter presents two improved bidirectional and low-voltage silicon-controlled rectifiers (BLVSCR-type1 and BLVSCR-type2), which are composed of two diode-triggered SCRs of opposite polarity in parallel. By improving the device structure and metal connection, the BLVSCR-type1 and BLVSCR-type2 can offer robust ESD capabilities. Compared with the conventional bidirectional direct-connected SCR (BDCSCR), experimental results show that the proposed BLVSCR-type1 can render a three order of magnitude reduction in the leakage current at a 1.2V I/O port and more stable parasitic capacitance characteristic. Moreover, the BLVSCR-type2 can possess a compact layout area reduced by as much as 35% when comparing to BLVSCR-type1.

The robustness of electrostatic sensitive devices is important in state-of-the-art silicon technology. However, the electrical breakdown-induced microstructure evolution remains unclear. In this work, we performed the physical failure analysis of breakdown in an enhanced modified lateral silicon-controlled rectifier-based electrostatic discharge (ESD) device. Direct visualization of the conductive metal filaments in the doped silicon substrate has been achieved by high-resolution transmission electron microscopy. The locations of these metal filaments induced by breakdown are found near the cathode. The evolution of these microstructural changes and chemical properties provides guide to the failure analysis of ESD devices.

Laterally Diffused Metal Oxide Semiconductor Silicon-Controlled Rectifier (LDMOS-SCR) is usually used in Electrostatic Discharge (ESD) protection. LDMOS-SCR discharges current by parasitic SCR, but the MOS in it cannot work when parasitic SCR is stabilized. To further enhance the Electrostatic Discharge (ESD) discharging capability of LDMOS-SCR, a novel high failure current LDMOS-SCR with 12 V operation voltage is fabricated and verified in a 0.18-um high-voltage Bipolar-CMOS-DMOS (BCD) process. Compared with conventional LDMOS-SCR, the novel LDMOS-SCR (LDMOS-SCR-R) introduced a heavily doped p-type region, which is located between the heavily doped n-type and p-type regions of Cathode and is connected with the gate. The adding p-well resistance can drop the voltage on the gate, and the gate with p-well resistance also has resistance and capacitance coupling effect. According to the results of the transmission line pulse test (TLP), the voltage applied to the gate by increasing the p-well resistance plays a major role in the device working mechanism. Under the same device size, LDMOS-SCR-R has higher It2 (8.6 A) than conventional LDMOS (2.21 A) or LDMOS-SCR (6.62 A) in TLP results. Compared with LDMOS-SCR, the failure current of LDMOS-SCR-R increases by 30 %, and the FOM of LDMOS-SCR-R increases by 34 %. The response of LDMOS-SCR-R is also faster than that of LDMOS-SCR under larger current conditions. In addition, the phenomenon in TLP results is consistent with simulation results. The proposed LDMOS-SCR-R can effectively increase failure current without affecting the device’s design window, and the additional p-type region will not increase the layout area.

System-level electrostatic discharge (ESD) noise due to electromagnetic fields radiating from an ESD generator were measured and analyzed in a solid-state drive (SSD) storage system. The field sour...

Electrostatic discharge (ESD) generators do not match each other, nor do the currents and fields from the discharge of a human via a piece of metal match those from ESD generators. A more realistic characterization of the field performance of a device under test (DUT) can be achieved using human subjects. To avoid using actual humans, while still achieving similar results, a full-size dummy has been designed. Its performance is verified by comparing it to currents and fields from human ESD and ESD generators.

A 900-MHz 1.2-V 4.36-mA low-noise amplifier (LNA) with a minimum of 0.92-dB noise figure (NF) at 868 MHz, −12-dBm IIP3, with one inductor (external) is demonstrated. The circuit achieves narrowband input matching on a wideband LNA without inductive degeneration. A new half-cascoding technique is used to improve the input matching ( $S_{11}$ ) while simultaneously achieving sub-1-dB NF performance. The 0.13- $\mu \text{m}$ CMOS LNA is fabricated with embedded electrostatic discharge (ESD) protection diodes that add 60- and 80-fF loads at the RF input and output ports. At 868 MHz, the packaged LNA has a measured input return loss ( $S_{11}$ ) of −18 dB and the transmission gain ( $S_{21}$ ) of 14.2 dB. At 900 MHz, the LNA has a measured NF of 0.98 dB. The LNA (excluding the buffer) occupies an area of 0.047 mm2. The chip passes the human body model (HBM) test with an ESD zap of 2.5 kV within 10% margin of its prezap $I$ – $V$ characteristics, under JEDEC standards. Multiple packaged chips were characterized with no perceptible difference in performance, indicating a robust design.

A modified cross-coupling low-triggering dual-polarity silicon controlled rectifier ( ${m}$ -CLTdSCR) for on-chip electrostatic discharge (ESD) protection is developed. Cross-coupling mechanism can effectively reduce the trigger voltage of the proposed structure. A lower leakage is achieved by replacing NMOS with PMOS and changed connection, and this also effectively reduces the parasitic capacitance of ${m}$ -CLTdSCR between anode and cathode. The new structure shows low-triggering voltage ~3.46 V, low leakage ~0.46 nA under normal operation condition, and low parasitic capacitance ~190 fF at zero bias. As such, the proposed ${m}$ -CLTdSCR is an attractive device for radio frequency integrated circuits (RFICs) ESD protection.

Antistatic packaging is largely used in the electronic industry to avoid damage in electronic components caused by electrostatic discharge (EDS), generated by friction during storage and transportation processes. Antistatic packages are commonly produced with electrically insulating polymeric matrices, indicating the need for the use of antistatic agents to impart dissipative properties to these materials and to permit the conduction of electrons through their structures. Carbon-based fillers like carbon black, graphite, glassy carbon, carbon nanotubes, and graphene have been successfully used for the production of polymeric composites with interesting and promising electrical properties, as it is indicated by the increasing numbers of works reported in the literature related to this research area in the past few years. In this way, this review article presents the latest advances related to the use of carbon-based materials in the development of new polymeric composites with dissipative properties, showing the recent approaches used for the production of antistatic packaging.

The integrated circuit (IC) products fabricated in the scaled-down CMOS processes with higher clock rate and lower power supply voltage (VDD) are more sensitive to the transient/switching noises on the power lines with the parasitic inductance induced by the bonding wire. The typical method to suppress the power line noise is to add on-chip decoupling capacitors. Meanwhile, electrostatic discharge (ESD) is also a challenging issue on IC reliability in advanced CMOS technology. For the ICs fabricated in an advanced process, with the thinner gate oxide, the circuits are particularly vulnerable to the charged-device model (CDM) ESD events. However, there was very limited research to investigate the ESD robustness on the decoupling capacitors, especially during the CDM ESD events. In this work, the CDM ESD robustness among different types of decoupling capacitors in ICs was investigated in a 0.18- ${\mu }\text{m}$ CMOS technology.

Traditional in-Silicon PN-junction-based on-chip electrostatic discharge (ESD) protection structures have inherent ESD-induced design overhead problems, including parasitic capacitance, leakage and Si area consumption. A potential solution to the ESD design overhead challenge is to use a non-conventional above-Si graphene-based nano-electrical mechanical system (gNEMS) transient switch structure to protect integrated circuits (ICs) against ESD failures. This paper reports investigation of materials and device structural impacts on gNEMS ESD protection structures. Transmission-line pulse (TLP) testing confirms that single-crystalline graphene gNEMS switch achieves a record high ESD current-handling capability of $\text{J}_{t2} {\mathbf {\sim }} 1.03\boldsymbol {\times } 10^{9}\text{A}$ /cm2, at least four times higher than $\text{J}_{t2} {\mathbf {\sim }} 0.24\boldsymbol {\times } 10^{9}\text{A}$ /cm2 for its poly-crystalline graphene counterpart. Transient 3D finite element method (FEM) simulation reveals that both device dimensions and shapes of the suspended graphene membranes can substantially affect gNEMS ESD discharging characteristics. The discovery offers guidelines for design optimization of gNEMS ESD switch structures.

Electrostatic discharge (ESD) robustness is an extremely important aspect in integrated circuits (ICs) and is well established for regular 2-D ICs. However, 2.5-D and 3-D integration present new challenges in both design and verification. While several studies have focused on design methodologies to achieve effective ESD protection in 2.5-D and 3-D ICs, there is a lack of research into automated ESD verification solutions for these technologies. Therefore, this article focuses on automated ESD verification in 2.5-D and 3-D ICs. We explain the verification challenges introduced by these integration technologies and propose an automated ESD verification methodology for 2.5-D and 3-D ICs. We implement this methodology in a programmable checker to automate the verification for complete 2.5-D and 3-D IC designs. The checker differentiates between external and internal inputs/outputs from the assembly level without the use of layout markers on the die level. It checks for correct, incorrect, and missing ESD protection circuitries for each category of inputs/outputs. It checks total parasitic resistance and performs current density analysis for the relevant interconnect routes through the entire 3-D IC design layout to ensure these routes can sustain the ESD event. We apply our proposed checker to a test case that includes 2.5-D and 3-D-specific ESD challenges and demonstrate its effectiveness.

The failure behavior and the corresponding physical mechanism of the AlGaN/GaN high electron mobility transistors (HEMTs) under transmission line pulse (TLP) stress were investigated in this paper. The result shows that the output and transfer characteristics of the AlGaN/GaN HEMTs after 90 cycles begin to degrade by comparing with the fresh ones under 40 V TLP voltage, and the gate leakage current of the devices slightly increases. When the TLP voltage of 52 V was applied, a catastrophic failure occurs for the AlGaN/GaN HEMTs. Furthermore, the failure of the AlGaN/GaN HEMTs was located, and the micro-morphology of the abnormal spot was observed. The result shows that the gate metal was damaged due to the large TLP stress. The failure mechanism may be mainly attributed to the Joule heat that causes the high lattice temperature of 1160 K as well as the electric field, and it is higher than the melting point of Au (1064 K) in the gate metal (Au/Ti/Mo). The results may be useful in the design and application of electrostatic discharge (ESD) for AlGaN/GaN HEMTs.

Charged device model (CDM) electrostatic discharge (ESD) protection is an emerging design challenge to ICs at advanced technology nodes. It was recently reported that the traditional pad-based CDM ESD protection methods are fundamentally faulty, which causes uncertainties in CDM ESD protection designs, testing and failure analysis. Re-thinking of on-chip CDM ESD protection becomes imperative for complex ICs implemented in advanced technologies. This paper reports a disruptive CDM ESD protection method utilizing non-pad-based internally-distributed ESD protection network as a robust in situ in-operando CDM ESD protection solution. The proposed internal-distributed CDM ESD protection mesh network can be realized using interposer or through-silicon-via (TSV) ESD protection structures to achieve local 3D CDM ESD protection via heterogeneous integration. The new concept was validated using an internal-CDM-protected oscillator IC implemented in a foundry 45nm silicon-on-insulator (SOI) technology.

Electrostatic discharge (ESD) transient events can often damage semiconductor components. Therefore, the ultrahigh-voltage (UHV) circular n-channel lateral diffused metal-oxide-semiconductor transistor (nLDMOS) usually used in power electronics needs to have ESD self-protection capabilities. In this paper, the geometric parameters of 300-V and 200-V UHV circular nLDMOSs were modulated using different layouts at the drain side. The high-voltage p-well (HVPW) layer was used to form various super junctions (SJs) in the drift region. The modulations were classified as SJ length, SJ concentration-gradient thickness, HVPW ring-sector, and rotated SJ concentration gradient modulations in the drift region. Various HVPWs were used to produce several SJs in the drain drift region. According to the final measurement results, all modulation processes maintained the original physical characteristics of high breakdown voltage. Devices with the SJ length and SJ concentration-gradient thickness’s modulations provided the best ESD robustness. The ESD testing value of the human-body model (HBM) will increase with the increase of the SJ length and SJ thickness modulations. The HBM value increased from the 1500 V reference to 4000V (increased by 166.66%).

The transport of high-speed data to and from chips requires input-output (I/O) interfaces with a commensurately wide bandwidth. In addition to the parasitic capacitances that the output driver in a transmitter (TX) and the input stage in a receiver (RX) present to the signal path, both interfaces must also deal with the capacitances associated with electrostatic discharge (ESD) protection devices. The I/O design thus becomes increasingly more challenging as greater speeds are sought. In this article, we design I/O circuits for a data rate of 40 Gb/s with a singleended voltage swing of 0.5 Vpp while focusing on the use of T-coils. The reader is referred to [1]-[5] for background information.

The ESD effects on the E-mode AlGaN/GaN high-electron mobility transistors (HEMTs) with p-GaN gate are investigated under repetitive TLP pulses. Firstly, the degradation and recovery of output, transfer characteristics, gate-leakage characteristics and low-frequency noises (LFN) are analyzed in detail before and after reverse electrostatic discharge (ESD) stress. The experimental results show that the electrical characteristics of the devices gradually degraded as the transmission line pulse (TLP) pules increased. Subsequently, the LFN measurements are performed over the frequency range of 1 Hz–10 KHz by increasing TLP pulses. Finally, the recovery tendency of DC (direct current) characteristics and trap density are studied and discussed after resting the device at room temperature for 1 to 3 months. These results physically confirm that the mechanism of the performance degradation and recovery of the devices could be attributed to the trapping and releasing processes of electrons in the p-GaN layer and AlGaN barrier layer of AlGaN/GaN HEMTs, which change the electric field distribution under the gate.

Electrostatic discharge (ESD) protection is a grand design challenge for complex ICs in advanced technologies. ESD simulation is indispensable to guide ESD protection designs. However, no existing ESD simulation methods may accurately predict ESD protection designs in a universal manner due to various inherent limitations. TCAD-based ESD simulation is very useful for ESD protection designs. Transmission line pulse (TLP) and very fast TLP (VFTLP) are widely used to evaluate human body model (HBM) and charged device model (CDM) ESD protection designs, which provide rich details for calibrating TCAD ESD simulation for design prediction and validation. Using various ESD protection devices fabricated in 28nm CMOS and 45nm SOI CMOS technologies, a comprehensive experimental and simulation study finds that the ESD stimuli used in TCAD ESD design simulation have profound impacts on many subtle ESD protection behaviors, particularly in comparison with ESD testing. This study cautions against over-interpretation of TCAD ESD simulation results, obtained using any specific ESD stimulus, attempting to accurately predict practical ESD protection designs. A mixed-mode multiple-stimuli ESD simulation method is therefore developed to address the ESD stimulus induced ESD performance variation, hence offering a technique to achieve ESD protection design prediction.

The ultra-high voltage (UHV) Lateral-diffused MOSFET (LDMOS) transistor has been widely used in power circuit applications and also used as an electrostatic discharge (ESD) self-protection device. However, the ESD ability of an UHV LDMOS is generally worse than that of low- and high-voltage (HV) devices, which means this UHV LDMOS device can be easily failed under an ESD event. Then, the method of embedded a silicon-controlled rectifier (SCR) into the HV LDMOS has been used in the HV circuit as an ESD protection technique. But when this architecture is applied to UHV devices, will its ESD capability be as good as in HV devices? A novel SCR with a P-body well architecture is proposed, which can effectively enhance the ESD ability of the UHV nLDMOS device when the drain side is embedded this new structure. The proposed structure can greatly improve the ESD capability of the device without adding any extra process step (& photomask), layout area and affecting the basic breakdown voltage. Finally, the proposed structure of the PPP-arranged type with the P-body well can greatly increase the ESD (FOM) ability which $\text{I}_{\mathrm{ t2}}$ and HBM ability can be increased by 68.7% and 22.2% (72.9%), respectively, as compared with the conventional SCR PPP-arranged type.

Dual-direction electrostatic discharge (ESD) protection devices can discharge both positive and negative ESD surges, owing to their excellent area efficiency. This study proposes a novel dual-direction MOSFET ESD protection device with a high holding voltage. Most existing dual-direction ESD protection devices are based on silicon-controlled rectifiers (SCR). Among them, the low triggering dual-directional SCR (LTDDSCR) has good trigger characteristics, but with low holding voltage. In contrast, the proposed high-holding-voltage dual-direction NMOS (HHDDNMOS) operates using two NPN parasitic bipolar transistors connected to the ESD discharge path and has a very high holding voltage and excellent snapback characteristics. The electrical and dual-directional characteristics of HHDDNMOS were analyzed using the transmission-line -pulsing system, and the latch-up immunity was verified by conducting transient-induced latch-up tests using the 0.18- $\mu \text{m}$ BCD process.

This article explores the scope of drain-extended FinFET (DeFinFET) as a high-voltage (HV) device contender for Fin-based SoC applications. For the first time, guidelines for efficient and reliable HV integration in sub-14 nm FinFET nodes are given. Up to what extent DeFinFET stands as a promising choice is carefully investigated through device-circuit interactions and reliability analysis of range of DeFinFET options. The same is then compared, in terms of radio frequency (RF)-power amplifier (PA) performance, dc–dc conversion efficiency, electrostatic discharge (ESD) robustness, and hot carrier immunity (HCI) reliability, with other HV alternatives in FinFET nodes and its planar counterpart, that is drain-extended MOS (DeMOS).

This article proposes a dual-directional silicon-controlled rectifier (SCR) with a novel structure and high holding voltage to improve the electrostatic discharge (ESD) design area efficiency in high-voltage environments. In terms of structure, by decreasing the emitter injection efficiency of the p-n-p parasitic bipolar transistor formed at the bottom of the gate region, the SCR positive feedback gain is reduced, which endows the proposed device with improved snapback characteristics compared with the conventional low-voltage triggering SCR (LVTSCR) and low-trigger dual directional SCR (LTDDSCR). This article conducted 2-D and mixed-mode simulations to compare and analyze the operating principles of the proposed and traditional devices. Additionally, experimental devices were fabricated under the same conditions using the 0.13- $\mu \text{m}$ process to verify their electrical properties and latch-up immunity by measuring the transmission line pulse (TLP) and transient latch-up (TLU). This article also conducted a detailed analysis on the optimization of electrical properties for the ESD design window of the proposed device according to the design variables and application of segment topology, and also analyzed the temperature reliability using a hot chuck control system. The measurement results reveal that the proposed device is highly suitable for the 12-V-class ESD design window, has improved reliability, and can provide excellent area efficiency in related applications.

In this letter, a new silicon-controlled rectifier (SCR) structure fabricated using 4H-SiC materials has been proposed and investigated. The proposed structure alleviates the strong-snapback phenomenon that occurs in the 4H-SiC SCR and demonstrates low trigger voltage and high holding voltage characteristics. The proposed device exhibits improved snapback characteristics with very high holding voltage against electrostatic discharge surges owing to the structural features and application of segment topology. It also has excellent on-resistance and improved thermal reliability owing to the physical characteristics of 4H-SiC. Traditional SCR and low-voltage trigger SCR (LVTSCR) are fabricated with 4H-SiC under the same conditions and their electrical characteristics are comparatively analyzed with those of the proposed SCR. This study also evaluates the electrical characteristics at high temperatures (300–500 K) to verify the high- temperature reliability of the proposed structure.

This study with the area-efficient design for improving electrostatic discharge (ESD) and Latch-up (LU) abilities in the ultra-high voltage (UHV) n-channel Lateral-Diffused MOSFET (nLDMOS) is investigated via a TSMC 0.5- $\mu \text{m}$ UHV Bipolar CMOS DMOS (BCD) process. There are two architectures of these nLDMOS devices with embedded Schottky diodes in the electrode area. Firstly, the drain side is divided into three concentric circles and embedded with Schottky diodes. The influence of these samples with different layout arrangements on ESD is evaluated. For the second item, UHV nLDMOS devices with the source side embedded Schottky diodes by two alternative layout types are developed. Experimental results showed that an UHV nLDMOS with embedded Schottky diodes at the drain side can significantly improve ESD ability, especially for the fully embedded Schottky diodes at the drain side (being with the highest figure of merit (FOM) value in the ESD, LU, and cell-area considerations). On the other hand, with embedded Schottky diodes at the source side can increase the holding voltage which can effectively improve the LU immunity.

A delay-locked loop (DLL), which is widely used to compensate for the timing of high-speed data communications, was designed and fabricated in a 180 nm CMOS process. The DLL integrated circuit was assembled on a simplified motherboard and the module structures of a laptop computer and was tested under electrostatic discharge (ESD) events. The input and output voltages of the DLL under ESD-induced noises were measured, and the average values of peak-to-peak jitter and jitter durations of the DLL clock were obtained from repeated measurements. The effects of the voltage-drain-drain (VDD) decoupling capacitors and a bias decoupling capacitor were investigated. SPICE simulations were conducted using the measured input voltages and were compared with the measured results. The root causes of the ESD-induced DLL jitter were identified by analyzing the waveforms from the SPICE simulations. Employing VDD decoupling capacitors and maintaining the amount of delay control parameters for delay cells in the DLL were crucial in reducing jitter. The measured ESD-induced VDD noises were also validated and analyzed using impedance parameter measurements.

In this letter, a novel, electrostatic discharge tolerant, semiconductor-based electro-explosive device was presented. The device which was called integrated semiconductor bridge (ISCB) chip consists of a monocrystalline silicon heating element, which was utilized to ignite pyrotechnic mix in weapon. Two planar transient suppression diode arrays were incorporated into the chip to protect against electrostatic discharge events. The characteristic of transient suppression diode array and electric discharge characteristic of the ISCB was tested by a capacitive discharge unit. Meanwhile, the behavior of the ISCB during electrostatic discharge events was also tested with a human body electrostatic discharge model. The results showed that the ISCB chip provided advantages including small size, fast ignition, electrostatic discharge insensitivity and low initiation energy applications.