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This paper describes a compact and low-power frequency synthesizer with quadrature phase output for software-defined radios (SDRs). The proposed synthesizer is constructed using a core phase-locked loop (PLL), which is coupled with a fractional-N injection-locked frequency divider (ILFD). The fractional-N injection-locking operation is achieved by the proposed self-synchronized gating injection technique. The principle of a fractional-N injection locking operation and the concept of the proposed circuits are described in detail. Analysis for predicting the locking range of the proposed fractional-N ILFD is investigated. A digital calibration scheme is adopted in order to compensate for process, voltage, and temperature (PVT) variations. Implemented in a 65 nm CMOS process, this work demonstrates continuous frequency coverage from 10 MHz to 6.6 GHz with quadrature phase output while occupying a small area of 0.38 mm 2 and consuming 16 to 26 mW, depending on the output frequency. The normalized phase noise achieves -135.3 dBc/Hz at an offset of 3 MHz and -95.1 dBc/Hz at an offset of 10 kHz, both from a carrier frequency of 1.7 GHz.

This paper presents a low-jitter, low-power and a small-area injection-locked all-digital PLL (IL-ADPLL). It consists of a dual-loop and a dual-VCO architecture in which one VCO (Replica) is placed in a TDC-less synthesizable ADFLL to provide continuous tracking of voltage and temperature variations. The other VCO (main) shares the control voltage with the replica VCO but is placed outside the loop and is injection-locked to lower its jitter and accurately set its frequency to the desired one. This approach avoids timing problems in the conventional ILPLL since the injection-locked VCO is placed outside the feedback loop. It also achieves a low power and a small area, due to the absence of a power hungry TDC and an area-consuming loop filter, while tracking any PVT variations. The IL-ADPLL is implemented in a 65 nm CMOS process and measurement results show that it achieves a 0.7ps RMS jitter at 1.2 GHz while having 1.6 mW and 0.97 mW power consumption with and without intermittent operation resulting in an FOM of -243 dB. It also consumes an area of only 0.022 mm2 resulting in the best performance-area trade-off system presented up-to-date.

This paper presents a 20 GHz push-push VCO realized by a 10 GHz super-harmonic coupled quadrature oscillator for a quadrature 60 GHz frequency synthesizer. The output nodes are peaked by a tunable second harmonic resonator. The proposed VCO is implemented in 65 nm CMOS process. It achieves a tuning range of 3.5 GHz from 16.1 GHz to 19.6 GHz with a phase noise of −106 dBc/Hz at 1 MHz offset. The power consumption of the core oscillators is 10.3 mW and an FoM of −181.3 dBc/Hz is achieved. key words: low phase noise, low power, tail-current modulation, impulse sensitivity function, super-harmonic coupled QVCO, push-push VCO

This paper proposes progressive mixing as a technique to widen the locking range of injection locked frequency dividers (ILFDs) with higher division ratios. The ILFD locking range for a certain division ratio depends on the harmonics that are used to generate the injection signal. Compared to the conventional ILFD, the proposed technique uses much stronger harmonics in the mixing process to generate the injection signal more efficiently for higher division ratios. This is achieved through the reuse of higher harmonics of the ILFD fundamental oscillation frequency to perform progressive or multisteps divide-by-2 mixing of the injection signal. This results in that the injection signal is mixed with much stronger harmonics compared to the conventional single-step mixing and a stronger injection is produced. Since each divide-by-2 step uses higher harmonics of the fundamental, there is no increase in power consumption while the locking range is significantly enhanced. Two progressive mixing ILFDs are designed using a 65-nm CMOS to divide-by-4 and divide-by-8. The former has an operation range from 7.3 to 21.3 GHz while maintaining a locking range greater than 31% and consuming 3.9 mW from a 1.2-V supply. The latter has an operation range from 12.6 to 24.7 GHz while maintaining a locking range greater than 15% and consuming 7.1 mW from a 1.2-V supply.

This paper presents a 60-GHz direct-conversion transceiver using 60-GHz quadrature oscillators. The transceiver has been fabricated in a standard 65-nm CMOS process. It in cludes a receiver with a 17.3-dB conversion gain and less than 8.0-dB noise figure, a transmitter with a 18.3-dB conversion gain, a 9.5-dBm output 1 dB compression point, a 10.9-dBm saturation output power and 8.8-% power added efficiency. The 60-GHz frequency synthesizer is implemented by a combination of a 20-GHz PLL and a 60-GHz quadrature injection-locked oscillator, which achieves a phase noise of -95 dBc/Hz@l MHz-offset at 60 GHz. The transceiver realizes IEEE802.15.3c full-rate wireless communication for all 16QAM/8PSK/QPSK/BPSK modes, and the communication distances with the full data rate using 2.16-GHz bandwidth, measured with an antenna built in the package, are 2.7-m (BPSK/QPSK) and 0.2-m (8PSK/16QAM). The measured maximum data rates are 8 Gb/s in QPSK mode and 11 Gb/s in 16QAM mode over a 5 cm wireless link within a bit error rate (BER) of

This paper proposes a 60 GHz quadrature PLL frequency synthesizer for the IEEE802.15.3c with wide tuning range and low phase noise. The synthesizer is constructed using a 20 GHz PLL that is coupled with a Quadrature Injection Locked Oscillator (QILO) as a frequency tripler to generate the 60 GHz signal. The 20 GHz PLL generates a signal with a phase noise that is lower than -105 dBc/Hz using tail feedback to improve the phase noise while having a 17% tuning range. The proposed 60 GHz QILO uses a combination of parallel and tail injection to enhance the locking range by improving the QILO injection efficiency at the moment of injection and has a 12% tuning range. Both the 20 GHz PLL and the QILO were fabricated as separate chips using a 65 nm CMOS process and measurement results show a phase noise that is less than -95 dBc/Hz@1 MHz at 60 GHz while consuming 80 mW from a 1.2 V supply. To the author's knowledge this phase noise is about 20 dB better than recently reported QPLLs and about 10 dB compared to differential PLLs operating at a similar frequency and at a similar offset.