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A two-step analog accumulator structure, fit for CMOS time-delay integration image sensor, is proposed to combat the impacts of parasitic phenomenon of the traditional one-step analog accumulator. To implement the two-step accumulation, the exposure signals are divided into groups. The synchronous signals in each group are integrated in step1 integrators, which are designed based on the switched-capacitor amplifier. Then, the integral signals from step1 are integrated in step2 integrators. The temporal undersampling exposure method is adopted in the sensor to reduce the number of integrators. Two versions of a prototype 64-stage two-step accumulator, with and without the decoupling capacitance $C_{d}$ , are designed and fabricated in 0.18- $\mu \text{m}$ one-poly four-metal 1.8 V/3.3 V CMOS technology. With an $8 \times 8$ stepping pattern, the signal-to-noise ratio improvements of the two versions are 17.278 and 17.192 dB at 64 stages, respectively, while the ideal value is 18.062 dB. The experimental results have proved the effectiveness of the two-step structure in combating the parasitic phenomenon and made the analog accumulator with higher stage realizable.

Based on the thermionic emission theory, a charge transfer model has been developed which describes the charge transfer process between a pinned photodiode and floating diffusion (FD) node for CMOS image sensors. To simulate the model, an iterative method is used. The model shows that the charge transfer time, barrier height, and reset voltage of the FD node affect the charge transfer process. The corresponding measurement results obtained from two different test chips are presented in this paper. The model also predicts that other physical parameters, such as the capacitance of the FD node and the area of the photodiode, will affect the charge transfer. Furthermore, the model can be extended to explain the pinning voltage measurement method and the feedforward effect.

A radiation hardened by design (RHBD) latch and its temporally hardened version to tolerate double node upsets are proposed in this paper. C-Elements are used to construct structures for fault correction. The temporally hardened version can further tolerate some single-event transients (SETs) at input port and clock line. Compared with Quintuple Modular Redundancy (QMR), the proposed non-temporally and temporally hardened latches are more area and power efficient with improved propagation delays. Compared with several previously reported temporally hardened latches, the proposed temporally hardened latch may introduce lower performance loss induced as setup time increase. Several multi-node upset tolerant latches are also compared with these two designs in terms of area, power, and delay. A cell level soft error analysis (TFIT) shows that the upset threshold LETs of the proposed latches in 180 nm process are higher than 16 MeV-cm2/mg.

This paper presents an in-pixel dual exposure synthesis technique to extend dynamic range of CMOS image sensors (CISs). The transfer transistor of the 4-T pixel acts as an overflow transistor in this proposed method. The full well capacity of photodiode (PD) can be very well controlled by biasing the transfer gate at different states. The long and short time exposed signals can be both stored in PD by adjusting the transfer gate voltage, and such the wide dynamic range signal can be obtained without extra readout operation. A proto chip with $64 \times 48$ pixel array is fabricated in 0.18- $\mu $ m CIS process. The sensor structure is based on a typical 4-T pixel image sensor with modified transfer gate driver and timing. This structure not only maintains the good features of 4-T pixels, such as good fill factor and low noise, but also achieves a wide dynamic range. The dynamic range of the proto chip is extended from 51.59 to 90.53 dB.

A quasi-constant on-time controlled buck front end in combined discontinuous conduction mode and boundary conduction mode is proposed to improve power factor (PF).When instantaneous AC input voltage is lower than the output bus voltage per period, the buck converter turns into buck-boost converter with the addition of a level comparator to compare input voltage and output voltage. The gate drive voltage is provided by an additional oscillator during distortion time to eliminate the cross-over distortion of the input current. This high PF comes from the avoidance of the input current distortion, thereby enabling energy to be delivered constantly. This paper presents a series analysis of controlling techniques and efficiency, PF, and total harmonic distortion. A comparison in terms of efficiency and PF between the proposed converter and a previous work is performed. The specifications of the converter include the following: input AC voltage is from 90V to 264V, output DC voltage is 80V, and output power is 94W.This converter can achieve PF of 98.74% and efficiency of 97.21% in 220V AC input voltage process.

The impacts of parasitic phenomenon on the performance of the analog accumulator in CMOS TDI image sensor are analyzed in this paper, and a modified accumulator with decoupling capacitor Cd to combat the parasitic phenomenon is also proposed. A 128-stage modified accumulator is designed and simulated. A prototype 1024 × 128 CMOS TDI image sensor with the 128-stage modified accumulator is fabricated in 0.18- μm one-poly four-metal 1.8 V/3.3 V CMOS technology. With a line rate of 3875 lines/s, at 128 stages the measured sensitivity and SNR improvement of the fabricated sensor are 617.1 V/lux·s and 16.6 dB respectively. The simulation and experiment results have proved the effectiveness of the decoupling capacitor C d when combating the parasitic phenomenon in the analog accumulator. The proposed modified accumulator is suitable for application in CMOS TDI image sensor with high stages.

Failure analysis on advanced logic and mixed-mode analog ICs more and more has to deal with so called ‘soft defects’. In this paper, a dynamic synchronization method is proposed to perform soft defect localization (SDL) technique by Optical Beam Induced Resistance Change (OBIRCH). It is a new and low-cost way to achieve SDL technique by OBIRCH equipment if there is no normal SDL equipment on hand. It extends the application of OBIRCH equipment to a more advanced failure analysis realm. The methodology and system configuration are presented. The experimental results show this dynamic synchronization method is accurate enough to locate a soft defect. Two real cases are studied on a digital IC and a mixed-mode analog IC respectively using this method.

This brief presents a 32-stage CMOS time delay integration image sensor with on-chip column parallel analog accumulator. Temporal oversampling technique is applied in the sensor to realize synchronous signal capturing. A column parallel analog accumulator with layout size of 0.09 mm2 is integrated at both sides of pixel array. Through adopting input-offset storing technique, a column fixed pattern noise because of the amplifier's offset variations is reduced by the accumulator. The accumulator also acts as a pixel noise canceller. The fabricated chip in 0.18- μm one-poly four-metal 1.8/3.3-V CMOS technology achieves the maximum line rate of 3875 lines/s. The measured signal-to-noise ratio of the fabricated sensor is improved on average by 11.9 dB at 16 stages and 14.2 dB at 32 stages. The presented sensor is suitable for application in low illumination, high scanning speed, and remote sensing systems.

A time error mathematical model is proposed to study the impact of nonlinear response and noises on imaging of time-based Pulse Width Modulation (PWM) pixel with the Correlated Double Sampling (CDS). The errors introduced by nonlinearity and certain noises, including fixed pattern noise (FPN), reset noise, shot noise and input-referred noise of pixel-level comparator, are studied. The relative error is impacted not only by the noise voltage, but also the comparator reference voltages, V refh and V refl . In the 0.18 μm CMOS process, the simulation result shows that the noises which have the largest impact on imaging are FPN and shot noise. The higher the V refh and V refl are, the smaller the error is introduced by FPN. The larger the difference between V refh and V refl is, the better the signal-to-noise ratio (SNR) is. The influence of reference voltage and clock frequency on dynamic range, and the trade-off between dynamic range and speed are also analyzed in this paper. Finally, the rules of reference voltage selection are discussed. The results can serve as a guideline to the design of the time-based PWM pixel with CDS.

A statistical model based on large sample simulation is established to study the relationship between random telegraph signal (RTS) noise and the number of time delay integration (TDI) stages in TDI CMOS image sensor (CIS). Matlab simulation results show that the mean value of RTS noise increases by a factor greater than M 0.5 when the number of TDI stages is M , and the factor approximates to M 0.5 with larger TDI stages. In noise histogram, RTS noise exhibits Gaussian distribution when the number of TDI stages is more than a special value. These results serve as a guideline for the design of TDI stages and the analysis of noise.

As the most popular nonlinear denoise technique, the median filter has attracted significant attention in recent years. In this paper, a novel adaptive median filter is presented to remove random-valued impulse noise in images, named Adaptive Partition-Cluster-Based Median (APCM) Filter. Based on the partition cluster idea, the noise detector classifies pixels into different groups and identifies the noisy pixels in different regions adaptively without iterations. According to the results of noise detection, an improved adaptive decision-based filter is presented to restore the pixels which are corrupted by random-valued impulse noise. The proposed filter technique is open to any impulse noise. Extensive simulation results demonstrate that the proposed method substantially outperforms other state-of-the-arts impulse noise filter techniques both visually and in terms of objective quality measures. Furthermore, the proposed method is much friendly to the hardware parallel implementation of image processing because of its low computation complexity and simple realizable structure.

With the further shrinking of IC dimensions, low- material has been widely used to replace the traditional SiO interlayer dielectric (ILD) in order to reduce the interconnect delay. The introduction of low- material into silicon imposed challenges on dicing saw process. ILD and metal layers peeling and its penetration into the sealing ring of the die during dicing saw are the most common defects. In this paper, the low- material structure and its impact on wafer dicing were elaborated. A practical dicing quality inspection matrix was developed to assess the cutting process variation. A 300-mm CMOS90-nm dual damascene low- wafer was chosen as a test vehicle to develop a robust low- dicing saw process. The critical factors (dicing blade, index speed, spindle speed, cut in depth, test pattern in the saw street, etc.) affecting cutting quality were studied and optimized. The selected C90 Dual damascene low- device passed package reliability tests with the optimized low- dicing saw recipe and process. The further improvement and solutions in eliminating the low- dicing saw peeling were also explored.

A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter (DAC) used for the ramp generator is based on the split-capacitor array with an attenuation capacitor. Analysis of the DAC's linearity performance versus capacitor mismatch and parasitic capacitance is presented. A prototype 1024 × 32 Time Delay Integration (TDI) CMOS image sensor with the proposed ADC architecture has been fabricated in a standard 0.18 μm CMOS process. The proposed ADC has average power consumption of 128 μW and a conventional rate 6 times higher than the conventional SS ADC. A high-quality image, captured at the line rate of 15.5 k lines/s, shows that the proposed ADC is suitable for high-speed CMOS image sensors.

Image blending plays an important role in video mosaicking, which has a high demand for real-time performance and visual quality. This paper proposes a fast blending method based on Bresenham algorithm, which realizes blending by controlling the storing addresses of source pixels. The starting storing location is accurately computed based on the coordinates of the middle pixel of the seam instead of the first pixel’s, reducing the accumulated error along the seam significantly. The other storing addresses are acquired using a variable-step Bresenham method, which takes advantage of burst mode operation of a dynamic memory and can achieve a good trade-off between the operation convenience and memory requirement. By the proposed method, complicated calculations of storing addresses are simplified into integer additions and subtractions, which is more suitable for hardware implementation. A hardware architecture based on field programmable gate array is presented to evaluate the proposed method with clock frequency analysis and resource assessment. The experimental results show that the proposed method achieves good performance of high image quality, low computational complexity, and low memory requirement.

A method to reduce the side effects of dual-line timed address-event (TAE) vision system is proposed in this paper. The side effects include edge discontinuity and the natural insensitivity to object edges in the motion direction. X-event, a kind of artificial event is introduced to represent light intensity difference perpendicular to the motion direction of the target object. New timestamps are attached to the raw TAE data to adjust temporary resolution to the same order of magnitude with the vertical axis in the TAE representation. After removing noisy and redundant events, designed templates are used to generate X-events to renovate broken lines and reproduce perpendicular edges. It is a real-time process which is unnecessary to wait for the collection of all the raw TAE data. A behavioral model of a 2 × 256 TAE vision sensor is established in Matlab, and X-events Generation block is realized in FPGA. Experimental results show that the proposed method can patch the TAE representation effectively to obtain a one-pixel-wide, precise, closed and connected contour.

In this paper, a CMOS digital pixel sensor (DPS) with pixel-level ADC based on pulse width modulation (PWM) scheme is proposed to overcome the restriction of low supply voltage imposed by device scaling trend. The pixel operates with a dynamic current comparison scheme to avoid using complex in-pixel comparator and achieve a high dynamic range (DR). By adjusting clock frequency for different illumination, DR is further extended due to increasing the maximum detectable photocurrent and lowering the minimum detectable photocurrent. The pixel contains a photodiode (PD), an 11-bit in-pixel SRAM and other 11 transistors, and occupies an area of 7 μm × 7 μm, with a fill factor of 31.3% using a standard 65 nm CMOS technology. Simulation results show that this pixel can work at a supply voltage as low as 0.5 V with 120 dB DR and 80 dB linear DR (LDR). The properties of high DR and logarithmic response make the proposed digital pixel be capable of human eye. Frame rate achieves 246 fps with 640 × 480 pixel array by using in-pixel ADC and SRAM. This makes the digital pixel very suitable for high-speed snap shot digital camera application.

In system level design or architecture design stage of SoCs, it is important to estimate the system parameters such as bus utilization and buffer capacity. A novel bus modeling method which was derived from Markov model for obtaining these parameters of an on-chip-bus system has been proposed in this paper. This modeling approach employs Markov chain to describe the state change of the system. This method was used in architecture design verification of a video format converting (VFC) chip. By comparing the simulation result and the pessimistic estimate value, the rationality and high efficiency of this method were verified, and more than 55% of FIFOs size are saved. It is suitable for analyzing various bus systems, such as user-defined buses, industrial standard buses, multi-core and multi-bus systems.

A multi-integration technology with compact readout method to extend CMOS image sensor's dynamic range is presented. Compared with the timing of rolling readout, compact readout extends the available pixel readout time by adjusting the time-domain offset between two adjacent rows and each integration time in one frame. Thus the column readout bus is working continuously rather than intermittently, which makes good use of the whole integration time and the available readout time can be extended. This dynamic range extension technology was implemented on a prototype chip with a 128 × 128 pixel array. The pixel readout time with compact readout method is almost as 3 times long as the one with rolling readout method while 39 dB dynamic range extension is achieved at 120 fps.

A current source circuit for high-resolution CMOS image sensors is introduced in this paper, which can provide a stable current with immunity from IR-drop along the power and ground wires. In the circuit, two pre-charged floating capacitors controlled by two-phase non-overlap clock are connected between the gate and source of a MOS transistor alternately to maintain a constant V GS of the MOS transistor. In this way, the current flowing through the MOS transistor will be stable and has nothing to do with power level. The post simulation results show that the current supplied by the proposed circuit decreases only by 1.6% when the voltage of the power supply decreases by 30%. The simulations have proved that the proposed circuit can improve the performance of high-resolution CMOS image sensors.

We present a field-programmable gate array (FPGA)-based hardware architecture for image processing as well as novel algorithms for fast autoexposure control and color filter array (CFA) demosaicing utilizing a CMOS image sensor (CIS). The proposed hardware architecture includes basic color processing functions of black-level correction, noise reduction, autoexposure control, auto-white-balance adjustment, CFA demosaicing, and gamma correction while applying advanced peripheral bus architecture to implement the hardware architecture. The speed of traditional autoexposure control algorithms to reach a proper exposure level is so slow that it is necessary to develop a fast autoexposure control method. Based on the optical-electrical characteristics of the CIS, we present a fast auto-exposure-control algorithm that can guarantee speed and accuracy. To ensure the peak SNR performance of the demosaiced images of the CIS and reduce the computational cost at the same time, the proposed demosaicing algorithm improves on the adaptive edge-sensitive algorithm and the fuzzy assignment algorithm. The experimental results show that the proposed hardware architecture works well on the FPGA development board and produces better quality images.