Search

Ceramic cultural relics have an important cultural value, and their detection technology plays a pivotal role in the protection of cultural relics. The traditional detection method of ceramic relics is based on X-ray technology, resulting in damage to the cultural relics. The terahertz-wave transmission is nondestructive; yet, the terahertz imaging has several technical problems, such as complex algorithms and unclear imaging. In this paper, we propose a terahertz-wave imaging system of a 0.2-terahertz operating frequency with a single input and single output and perform the transmission imaging experiment of the ceramic container. This design adopts the iterative threshold segmentation imaging method to obtain the high-quality transmission image and the neural network algorithm in the imaging recognition. Both the imaging and identification results effectively prove excellent performance, such as the high efficiency, high precision, and good reliability of the nondestructive testing system for the ceramic relics. The resolution can reach 2 mm, and the time for imaging identification can be

This paper presents a single-pole 32-throw (SP32T) switch with an operating frequency of up to 6 GHz for 5G communication applications. Compared to the traditional SP32T module implemented by the waveguide package with large volume and power, the proposed switch can significantly simplify the system with a smaller size and light weight. The proposed SP32T scheme utilizing tree structure can dramatically reduce the dc power and enhance isolation between different output ports, which makes it suitable for low-power 5G communication. A design methodology of a novel transmission (ABCD) matrix is proposed to optimize the switch, which can achieve low insertion loss and high isolation simultaneously. The average insertion loss and the isolations are 1.5 and 35 dB at 6 GHz operating frequency, respectively. The switch exhibits the measured input return loss which is better than 10 dB at 6 GHz. The 1 dB input compression point of SP32T is 15 dBm. The prototype is designed in 5 V 0.25 μm GaAs technology and occupies a small area of 12 mm2.

A detailed theoretical derivation and calculation method of the difference coefficient between a light distribution pattern of a 30 × 20 µ m 2 green micro-LED array and Lambert source is proposed first in this paper, to the best of our knowledge, which establishes an accurate relationship between external quantum efficiency and current efficiency (cd/A). The variation of capacitance with voltage and wavelength blueshift is illustrated by a carrier recombination mechanism. The current efficiency reaches 132.5 cd/A for the 60 × 50 µ m 2 and 121.7 cd/A for the 25 × 15 µ m 2 arrays, and the mechanism caused by size dependence is analyzed in detail combined with the classical ABC model.

This article describes an asynchronous split-CDAC-based SAR ADC with integrated input PGA and an RV-Buffer. The split CDAC structure not only reduces the area of the ADC, but also relieves the driving pressure of the input PGA and RV-Buffer. Using the input PGA instead of the traditional input buffer as the driving circuit of the ADC increases the dynamic input range of the ADC. The proposed on-chip RV-Buffer can provide 1.1 V positive and 0.1 V negative voltage, avoiding the disturbance caused by off-chip reference. This prototype is implemented in a 65 nm CMOS process and occupies an active area of 0.088 mm2. The input PGA can provide 0–18 dB programmable gain with a step of 3 dB. Measurement results show that as the provided gain changes, the ADC’s SNR is best, reaching 50.9 dB, and the SFDR is beat, reaching 62.35 dB at 50 MS/s.

Triggered by the pioneering research on graphene, the family of two-dimensional layered materials (2DLMs) has been investigated for more than a decade, and appealing functionalities have been demonstrated. However, there are still challenges inhibiting high-quality growth and circuit-level integration, and results from previous studies are still far from complying with industrial standards. Here, we overcome these challenges by utilizing machine-learning (ML) algorithms to evaluate key process parameters that impact the electrical characteristics of MoS2 top-gated field-effect transistors (FETs). The wafer-scale fabrication processes are then guided by ML combined with grid searching to co-optimize device performance, including mobility, threshold voltage and subthreshold swing. A 62-level SPICE modeling was implemented for MoS2 FETs and further used to construct functional digital, analog, and photodetection circuits. Finally, we present wafer-scale test FET arrays and a 4-bit full adder employing industry-standard design flows and processes. Taken together, these results experimentally validate the application potential of ML-assisted fabrication optimization for beyond-silicon electronic materials., Here, the authors demonstrate the application of machine learning to optimize the device fabrication process for wafer-scale 2D semiconductors, and eventually fabricate digital, analog, and optoelectrical circuits.

This paper presents a broadband frequency quadrupler (FQ) implemented with a standard 130-nm SiGe BiCMOS process. Two broadband push-push frequency doublers (×2) operate at an input frequency of 32.5–55 GHz and 65–110 GHz, respectively. To properly drive the two doublers with enough input power and bandwidth, two transformer coupled power amplifiers (PAs) have been adopted. The former power amplifier is based on a neutralized capacitor structure and the latter is based on a transformer topology. A nonlinear device model and a systematic methodology to generate maximum power at second harmonic are proposed. By manipulating the device nonlinearity and optimizing the magnetically and capacitively coupled resonator (MCCR) matching networks, optimum conditions for harmonic power generation are provided. The measurement results show that the proposed quadrupler provides a 90-GHz bandwidth with an 80-dB dynamic range and a high energy efficiency η of 3.7% at 210 GHz.