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The program/erase (P/E) cyclic endurances including bias temperature instability (BTI) behaviors of Metal-Al₂O₃-Nitride-Oxide-Semiconductor (MANOS) memories are investigated in comparison with those of Semiconductor-Oxide-Nitride-Oxide-Semiconductor (SONOS) memories. In terms of BTI behaviors, the SONOS power-law exponent n is ~0.3 independent of the P/E cycle and the temperature in the case of programmed cell, and 0.36~0.66 sensitive to the temperature in case of erased cell. Physical mechanisms are observed with thermally activated h * diffusion-induced Si/SiO₂ interface trap (N IT ) curing and Poole-Frenkel emission of holes trapped in border trap in the bottom oxide (N OT ). In terms of the BTI behavior in MANOS memory cells, the power-law exponent is n=0.4~0.9 in the programmed cell and n=0.65~1.2 in the erased cell, which means that the power law is strong function of the number of P/E cycles, not of the temperature. Related mechanism is can be explained by the competition between the cycle-induced degradation of P/E efficiency and the temperaturecontrolled h * diffusion followed by N IT passivation.

The electrical properties of Cr-SrTiO"3 films deposited on p-Si(100) substrates are investigated for application to a new type of charge-trap flash memory, named ReCTF (ReRAM+CTF). The Cr-SrTiO"3 film used as a switch in a ReCTF device has a complete cubic perovskite structure with a (200) crystallographic orientation. By means of current-voltage (I-V) and capacitance-voltage (C-V) analyses, we found that it exhibited electric-field-induced threshold switching characteristics and there were no trapping effects. In this study, we investigated how the retention characteristics of the ReCTF device can be improved without any special processes by applying an optimized Cr-SrTiO"3 film.

We report the effect of hydrogen annealing on the gate-leakage-current and switching characteristics of metal-alumina-nitride-oxide-silicon (MANOS) capacitors by analyzing their negative-/positive-bias instability (NBI/PBI). One sample, namely, A, is annealed with rapid thermal annealing (RTA), and the other sample, namely, B, is first annealed with RTA and then further annealed in a furnace, using a N2-H2 (98% nitrogen and 2% hydrogen) gas mixture. In the NBI/PBI experiments, the flatband voltage shift ΔVFB is observed to be smaller, i.e., the gate-leakage-current density is reduced for sample B at gate voltages less than ±3 V, a domain where trap-assisted tunneling is dominant. However, ΔVFB increases rapidly for the same sample at gate voltages larger than ±6 V, a domain where the modified Fowler-Nordheim tunneling (MFNT) is dominant, which indicates faster program-and-erase characteristics. These results show that additional hydrogen annealing can improve both device reliability and switching characteristics of the MANOS-type memory by reducing interface traps between the silicon substrate and silicon oxide layers, as well as turn-on voltages for MFNT.

The paper presents the passivation effect of post-annealing gases on the negative bias temperature instability of metal/silicon-oxide/silicon-nitride/silicon-oxide/silicon (MONOS) capacitors. MONOS samples annealed at 850 °C for 30 s by a rapid thermal annealing (RTA) are treated by additional annealing in a furnace, using annealing gases N 2 and N 2 –H 2 (2% hydrogen and 98% nitrogen gas mixture) at 450 °C for 30 min. MONOS samples annealed in an N 2 –H 2 environment are found to have lowest oxide trap charge density shift, Δ N ot = 8.56 × 10 11 cm −2 , and the lowest interface-trap density increase, Δ N it = 4.49 × 10 11 cm −2 among the three samples as-deposited, annealed in N 2 and N 2 –H 2 environments. It has also been confirmed that the same MONOS samples have the lowest interface-trap density, D it = 0.834 × 10 11 eV −1 cm −2 , using small pulse deep level transient spectroscopy. These results indicate that the density of interface traps between the silicon substrate and the tunneling oxide layer are significantly reduced by the additional furnace annealing in the N 2 –H 2 environment after the RTA.

ZnO-based charge-trap Flash technology using a resistive switching mechanism is demonstrated for next-generation nonvolatile memory. This device consists of metal/ZnO/nitride/oxide/silicon in order to make use of the electrical transport in the ZnO resistive switching layer. Compared to the previous devices with perovskite oxide materials used as a conduction path, the proposed device shows faster switching speeds (10 ns/100 μs), lower operation voltages ( ±7 V) for the program/erase ( P/E) states, and higher endurance (106 P/E cycles), along with comparable retention properties.

This letter covers the fabrication of a transparent resistive random access memory (T-ReRAM) device using ITO/AlN/ITO capacitors and its observed resistive switching characteristics. This AIN-based T-ReRAM shows a transmittance above 80% (including the substrate) in the visible region and an excellent switching behavior under ±3 V/10 ns with a high-to-low resistance ratio greater than 102. In the reliability test, the device showed an endurance of >; 108 cycles and a retention time of >; 105 s at 85°C. We believe that the AIN-based T-ReRAM presented in this letter could be a milestone for future see-through electronic devices.

An effective resistive-switching effect has been observed in silicon nitride (Si3N4) dielectrics in Ag/Si3N4/Al memory cells. The ratio of the low resistance to high resistance state was larger than 107 at ±1.2 V for a 10 nm thick Si3N4 layer. This switching behavior is attributed to a change in the conductivity of the Si3N4 dielectrics, depending on whether nitride-related traps are filled with electrons under positive biases or unfilled under negative biases. This assertion is experimentally confirmed from the relationship between the amount of charges trapped in the Si3N4 layer and the corresponding changes in its resistance with respect to bias voltages. In addition, the formation or dissolution of the conductive path is confirmed by conductive atomic force microscopy current images.