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To minimize the average latency of users to complete tasks, this letter jointly optimizes offloading decision, computation and bandwidth resource allocation for Mobile Edge Computing (MEC) networks via partial offloading. Since the considered problem is strongly non-convex with coupled variables, we decompose the original problem into two subproblems: (1) offloading decision; (2) communication bandwidth and computation resources allocation, and further employ Block Coordinate Descent (BCD) method to tackle them sequentially with linear computation complexity. Simulation results demonstrate that the proposed algorithm can achieve better performance on the average latency, and converge speedily.

NAND flash-based solid-state drives (SSDs) have been widely used in consumer electronic products such as smartphones, digital video recorders, and laptops. The flash translation layer (FTL) is crucial to the performance of SSDs. In this article, an on-demand FTL, briefly as HDFTL, is proposed for hybrid SSDs built with SLC+MLC flash memory. HDFTL divides the SLC into data blocks and translation blocks and uses all MLC as data blocks. All mapping items are stored in the translation block of the SLC, and partial mapping items are loaded into the cached mapping table of the FTL as needed. The contributions of HDFTL are as follows: (1) Unify the address mapping method of SLC and MLC areas to simplify the FTL design of hybrid SSDs; (2) Split the cached mapping table into a hot-write mapping table and a normal mapping table and use time locality to solve hot-write identification problem in hybrid SSDs; (3) According to the relative wear rate of SLC and MLC areas, adaptively adjust the size of the hot-write mapping table and the normal mapping table. Experimental results show that the performance of HDFTL is better than that of the existing FTLs for hybrid SSDs.

Because of the excellent performance and decreasing price of NAND flash, NAND flash-based solid-state drive (SSD) has been widely used as a storage system in consumer electronics. Moreover, modern consumer SSDs usually adopt a multichannel parallel structure. Thus, how to fully utilize the internal parallelism through IO scheduling is a key problem. The existing IO schedulers fail to solve the following: 1) the utilization of flash translation layer information to optimize the internal parallelism is not sufficient; 2) the wear of flash memory is not considered when allocating write requests. This article proposes a Wear-aware Out-of-order Dynamic Scheduling Algorithm (WODSA). First, according to the information of the flash translation layer, the max-parallel-based scheduling strategy is proposed to schedule the read requests to maximize read parallelism. Second, the wear-aware dynamic write allocation strategy is proposed based on the idle/busy state and wear degree of channels and chips. WODSA allocates write requests to channels and chips with less wear preferentially in a maximized parallel manner to achieve write parallelism and active dynamic wear-leveling. Experimental results show that compared with existing IO schedulers and dynamic wear-leveling algorithms, WODSA can improve both the average response time and wear-leveling in block-level and channel-level.

As an infrastructure-free positioning and navigation method, pedestrian dead reckoning (PDR) is still a research hotspot in the field of indoor localization. Step detection (SD) and stride length estimation (SLE) are two key components of PDR, and it is a challenging problem to apply SD and SLE to different walking patterns. Focusing on this problem, this paper proposes a robust SD and SLE method based on recognizing three walking patterns (i.e., Normal Walk, March in Place, and Quick Walk) using a smartphone. First, we propose a dynamic time warping–based peak prediction with zero-crossing detection to improve the SD accuracy. In particular, the proposed SD can accurately identify the starting and ending points of each step in the three walking patterns. Second, according to the extracted features of each step, a random forest algorithm with classification proofreading is used to recognize the three walking patterns. Finally, an improved SLE model is proposed for the different walking patterns to achieve a higher SLE accuracy. The experimental results show that, on average, the SD accuracy is about 97.9%, the recognition accuracy is about 98.4%, and the relative error of the estimated walking distance is about 3.0%, which outperforms those of the existing commonly used SD and SLE methods.

Traditional distance-based location verification system (LVS) is ineffective for some attacks in sparse mobile ad hoc networks, e.g., the similar distance-based malicious (SDM) attack. In this letter, we propose to exploit radio irregularity to build a novel LVS. Our system detects attack based on the estimated difference of radio irregularity coefficients and the claimed locations of the malicious node and an assistant node. To the best of our knowledge, our system is the first-of-its-kind that can detect SDM attack and pollution attack with only the received signal strength indicator information transmitted by a detecting node to the suspicious malicious node and an assistant node. Simulation results demonstrate that our proposed system can detect the attacks that cannot be detected by traditional distance-based methods.

Localization problem is an important and challenging topic in today's wireless sensor networks. In this paper, a novel localization refinement algorithm for LAEP, which is a range-free localization algorithm by using expected hop progress, has been put forward. The proposed localization refinement algorithm, called as CVLR, is based on position correction vectors and can resolve the LAEP's hop-distance ambiguity problem, which can lead to adjacent unknown nodes localized at the same or very close positions. CVLR can make full use of the relative position relationship of 1-hop neighboring nodes (called as CVLR1), or 1-hop and 2-hop neighboring nodes (called as CVLR2), to iteratively refine their localization positions. Furthermore, from localization accuracy and energy dissipation perspective, we optimize the communication process of CVLR2 and propose an energy-efficient improved CVLR. Simulation results show that the localization accuracy of CVLR1, CVLR2, and the improved CVLR are obviously higher than that of LAEP and DV-RND.

This paper proposes an object oriented model scheduling for parallel computing in media MultiProcessors System on Chip (MPSoC). Firstly, the Coarse Grain Data Flow Graph (CGDFG) parallel programming model is used in this approach. Secondly, this approach has the feature of unified abstraction for software objects implementing in processor and hardware objects implementing in ASICs, easy for mapping CGDFG programming on MPSoC. This approach cuts down the kernel overhead and reduces the code size effectively. The principle of the oriented object model, the method of scheduling, and how to map a parallel programming through CGDFG to the MPSoC are analyzed in this approach. This approach also compares the code size and execution cycles with conventional control flow scheduling, and presents respective management overhead for one application in media-SoC.

This paper proposes general software optimization techniques for embedded systems based on processors, which mainly include general optimization methods in high language and software and hardware co-optimization in assembly language. Then these techniques are applied to optimize our MP3 decoder, which is based on RISC32, a RISC core compatible with MIPSI instruction set. The last optimization decoder requires 48 MIPS and 49 Kbytes memory space to decode 128 Kbps, 44.1 KHz joint stereo MP3 in real time with CPI 1.15, and we have achieved performance increase of 46.7% and memory space decrease of 38.8% over the original decoding software.