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This letter presents an ultrawideband 7-bit digital-step attenuator (DSA). Capacitive compensation technique is utilized to improve the amplitude and phase accuracy and enable wideband operation. The attenuator is implemented in a 55-nm CMOS process and occupies 0.044-mm² core area. It demonstrates a 15.9-dB attenuation range with a 0.125-dB step size. The measured insertion loss (IL) is 2.7-6.6 dB at dc-28 GHz and the rms amplitude and phase errors of four measured chips are

This article presents a 7-bit wideband passive attenuator with low insertion loss (IL) and high attenuation accuracy in 55-nm CMOS technology. The $\pi $ -type and bridge-T-type attenuation units utilize an effective capacitive compensation technique, whose bandwidth extension mechanism is detailed in a single-unit pole–zero analysis. The matching-induced performance deterioration is investigated to minimize amplitude and phase errors at the chip level. The fabricated attenuator demonstrates a 32.4-dB attenuation range with a 0.255-dB resolution and a 3.5–8.4-dB IL from dc to 32 GHz. The measured root-mean-square (rms) amplitude and phase errors are below 0.32 dB and 5.33°, respectively. The attenuator occupies a 0.054-mm2 core area and consumes negligible power.

This article presents a wideband balanced variable-gain low-noise amplifier (VG-LNA) implemented in a 55-nm CMOS process. The proposed LNA has two cascode stages with an interstage matching transformer to constitute a fourth-order magnetically coupled resonator with two resonant peaks. The frequency-selective gain equalization technique is proposed to compensate for the gain variation of interstage dual-resonant tanks. This VG-LNA leverages a current-steering technique to realize a phase-invariant 18-dB tunable gain range with a measured input 1-dB gain compression point (IP $_{\mathrm {1\,dB}}$ ) at 9 GHz from −12.2 to −5 dBm. The LNA achieves a power gain of 20.2 dB with ±0.5-dB gain variation and a noise figure (NF) of 3.26 dB from 6.5 to 12 GHz. Due to the lumped Lange couplers, the input and output matching are both better than −14 dB. This chip occupies $1.44\times0.68$ mm2 area excluding pads and consumes 75 mW.

A true-time-delay-based (TTD-based) receiver front end with 800-ps time delay for 6.5–9-GHz wideband phased arrays has been designed for satellite communication in a 65-nm CMOS technology. The proposed receiver front end consists of a balanced low-noise amplifier (LNA), a 6-bit attenuator with 15.75-dB tuning range, a programmable TTD element featuring 800-ps delay with 25-ps delay step, and an output buffer amplifier. A differential origami inductor is proposed to boost the delay unit’s quality factor and mitigate the insertion loss introduced by the artificial transmission line (ATL). A current-mode radio-frequency (RF) multiplexer is designed to ensure a rapid delay switching. The receiver front end demonstrates a 3.6-dB noise figure (NF) with an 18-dB typical gain and an input 1-dB compression point (IP1dB) of −17 dBm at 6.5–9 GHz. This TTD element allows for a low insertion loss and a small chip area per unit time delay of ATL-based RF TTDs.