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Perkembangan teknologi saat ini sangatlah berkembang dengan pesat, komunikasi sangat penting dan dibutuhkan, Peneltian ini bertujuan untuk merancang bangun sebuah perangkat Duplexer yang bekerja pada band 900 MHz pada jaringan radio hybrid. Duplexer adalah perangkat yang menggunakan satu antena pada frekuensi yang berbeda. Pada penelitian ini menggunakan metode kuantitatif, karena hanya satu antenna yang dapat berkomunikasi antara dua HT, duplexer didesain menggunakan mikrostrip sebagai resonator. Komponen L dan C pada mikrostrip ini menggunakan teknik open circuit untuk kapasitor dan short circuit untuk induktor. Duplexer diperoleh dengan memanfaatkan respon frekuensi band stop filter (BSF). Frekuensi yang digunakan pada band 900 Mhz yang mana frekuensi uplink adalah 453,025 MHz – 463,025 MHz dan frekuensi downlink 458.025 MHz – 468.025 MHz.Hasil pengujian diperoleh redaman pada cut off mencapai 12 db. Redaman ini merupakan tingkat isolasi sinyal antara sinyal uplink dan downlink.

There has been significant recent progress in the implementation of integrated non-reciprocal components based on linear periodically time-varying (LPTV) circuits. Nevertheless, integrated circulators still require a leap forward in power handling, clock power consumption, and insertion loss (IL) to become compelling compared with ferrite circulators or integrated reciprocal alternatives, such as the electrical-balance duplexer (EBD). This article introduces three innovations: 1) a new switched-capacitor clock-boosting scheme; 2) high-Bragg-frequency quasi-distributed transmission lines based on periodically loaded inductors; and 3) a new gyrator based on switched partially reflecting t-lines—which enable significant performance improvement for integrated circulators and for LPTV circuits more broadly. These are showcased in a 1-GHz 180-nm SOI CMOS circulator that exhibits 2.1-/2.6-dB TX-ANT/ANT-RX IL (0.3 dB better than prior art), +34-dBm TX-ANT P1 dB (2.5 $\times $ or 4 dB better), and 40% lower chip area, all at 39-mW power consumption (4.4 $\times $ lower).

A new ultra-wideband millimetre-wave passive balanced duplexer (DUX), employing a lumped-element Wilkinson power divider and grounded-centre-tap transformer, has been developed using 0.18- μ m BiCMOS process for fifth generation operations at 28, 37, 39 GHz, and beyond. The developed DUX is configured single-ended transmitter (TX) and antenna (ANT) ports and differential receiver (RX) port. It has an inherent matching at TX, RX and ANT ports, high TX–RX isolation, and highly balanced differential RX waveforms, and is ready for direct integration with a differential low-noise amplifier. Analysis has been performed to confirm the DUX's characteristics and assess its performance. Measured isolation from TX to each single-ended RX port is higher than 50 and 40 dB from dc-20 GHz and dc-60 GHz, respectively. Measured insertion loss from TX to antenna is better than 6.3 dB across 13–53 GHz. Measured insertion loss from ANT to differential RX port is lower than 13.8 dB from 25 to 57 GHz with 10.8 dB at 40 GHz. The core chip only occupies 0.3 mm2.

In this article, a body channel communication (BCC) transceiver (TRX) and low-power receiver (RX) that can cover wide applications are proposed. The IEEE 802.15.6 human body communication (HBC) physical layer (PHY) standard and high-speed data transmission are supported simultaneously with a single chip. First, the sinusoidal-modulated transmitter is proposed for the standard mode TRX, and it can reduce filtering power overhead 35%. Second, high-speed TRX is proposed that can support dual-band QPSK modulation to increase system data rate and bandwidth efficiency. Third, on-chip RC duplexer is proposed for full-duplex function in communication. Also, for the low-power RX, a wireless power transfer (WPT)-based wake-up receiver (WuRX) and a higher energy efficiency main RX is integrated into RX chip. The main HBC RX demodulates both ASK and frequency-shift keying (FSK) information with a sharing oscillator (OSC) with 31- $\mu \text{W}$ low-power consumption. The TRX and RX are implemented in 65-nm CMOS process.

This study presents the first monolithically integrated full-duplex front-end for K/Ka satellite communication phased arrays. A 0.25 μm SiGe:C BiCMOS process was used to develop the integrated circuit. The receive and transmit channels are united into a common port through a novel duplexer. For each RF channel, the bias currents, the active channels and the power amplifier operation mode can be controlled through a serial bus. Amplitude and phase control are provided with fine granularity (65,536 states). In transmit mode, each channel provides 37.3 dB of gain with 12.9 dBm output power at 1-dB compression. In receive mode, 33.7 dB gain is measured with a noise figure of 3.2 dB. The amplitude/phase root-mean-square errors within the transmit (29.5–30.8 GHz) and receive (19.7–21 GHz) bands are below 0.7 dB/ 6.4 ° and 0.26 dB/ 1.1 ° , respectively. The chip occupies 1.64 × 3.5 m m 2 and it consumes 81 and 15.5 mW per transmit and receive channels, respectively. The use of a Doherty power amplifier with a novel dynamic adaptive bias circuit led to a 31% reduction of the total dc array power consumption.

A 220GHz communication system is designed and manufactured.For applications in space-distributed satellite networks, 5Gbps code rate level 100m communication is realized between satellites under THz carrier frequency.The system carrier frequency covers 210GHz to 230GHz. The baseband signal at the transmitter side is modulated directly on the carrier, multiplied and then mixed with the modulated signal before transmitting. At the receiving end, the signal is received by the antenna and output by the duplexer to a LNA, then down-converted to the IF unit after frequency doubling and harmonic mixer, and demodulated at IF to output the I/Q baseband signal to the signal processing unit.

In this paper, we present a phased-array transceiver chip operating in full X-band (8-12 GHz) in 65-nm CMOS technology. The presented transceiver for the transmit/receive module (TRM) consists of a 6-bit passive phase shifter, a 6-bit attenuator, a bi-directional gain amplifier (BDGA), and a single pole double throw (SPDT) switch connected to the internal power amplifier (PA) and the low-noise amplifier (LNA) to serve as a duplexer. A 64-bit SPI scan-chain is integrated for digital TRM control. The transmitter achieves greater than 15 dB of power gain with 11.84 dBm at the output 1-dB compression point (OP1dB). To achieve a wideband operation of the passive phase shifter, we assigned two different resonant frequencies for the phase leading and lagging networks and aligned the slopes of their phase responses to have the desired phase shifts at the center frequency. The RMS phase error is less than 5°, and the RMS amplitude error is less than 0.45 dB for all phase and attenuation states within 8-12 GHz while dissipating 216 mW dc power from a 1 V power supply. The receiver shows greater than 15 dB of power gain and has a noise figure (NF) of less than 8.4 dB for the entire X-band. The RMS phase error and the RMS amplitude error are less than 5° and 0.45 dB, respectively, for all control states within 8-12 GHz. The receiver consumes 110 mW with a 1 V power supply. The transceiver chip occupies an area of $4\times1.88$ mm2.

This paper describes the design of an integrated duplexer with electrical balance network using the phase locked loop (PLL) for impedance variation tracking. The hybrid transformer is devised for blocking the transmitted signal leaking to the receiver. We suggest a method of impedance tracking based on PLL system, which can maintain high isolation between the transmitter and the receiver. The PLL is employed to sense the transmitter leakage continuously and tune the impedance of the electrical balance network adaptively in real time. The isolation between the transmitter and the receiver is maintained almost constantly in a range of capacitances used in the antenna model, compared with that without the phase locked loop. The return loss at the transmitter port and the insertion loss from the transmitter to the antenna port are measured 30 dB and 6.9 dB at 1.95 GHz, respectively. The planar inverted-F antenna (PIFA) model is used for simulating and measuring antenna and electrical balance network. A capacitor value comprising the PIFA is varied and the proposed duplexer is investigated, leading to automatic impedance tracking in some range.

This paper presents a (transceiver) TRX front-end structure design for Phased Array applications in 40nm CMOS Bulk process. The proposed structure consists of the Power Amplifier (PA) the Low Noise Amplifier (LNA) along with a monolithic transformer duplexer for Antenna connection applied in half-duplex systems. The front end covers the millimeter wave (MMW) 5G band. The PA design contains two differential cascode stages with capacitor neutralization technique achieving a small signal gain (S 21 ) of 22.86dB with a -3dB bandwidth (BW) at 22-34 GHz. Moreover, the PA reaches a PAE max of 31.66% and a P sat of 18.5 dBm. The LNA design consist of two cascode stages using current reuse technique at the first stage, obtaining 17.5 dB gain (S 21 ) with a -3 dB bandwidth from 22.5 to 31 GHz. Both amplifiers are connected to the antenna through a compact duplexer with minimum losses and sufficient isolation.

There has been significant recent progress in the implementation of integrated non-reciprocal components based on linear periodically-time-varying (LPTV) circuits [1], [5]. Nevertheless, integrated circulators still require a leap forward in power handling, clock power consumption, insertion loss (IL), and chip area to become compelling when compared with ferrite circulators or integrated reciprocal alternatives, such as the electrical-balance duplexer (EBD) [6]. This paper introduces three innovations - (i) a switched-capacitor clock-boosting scheme, (ii) high-Bragg-frequency quasi-distributed T-lines based on periodically loaded inductors, and (iii) a gyrator based on switched partially reflecting T-lines - that enable such a leap for integrated circulators and for LPTV circuits more broadly. These are showcased in a 1GHz 0.18µm SOI CMOS circulator that exhibits 2.1/2.6dB TX-ANT/ANT-RX IL (0.3dB better than prior art [4]), +34dBm TX-ANT P1dB (2.5x or 4dB better), and 40% lower chip area, all at 39mW power consumption (4.4x lower).

Electrical balance-based full-duplex front-end allows high power operation but has strong tradeoff between Tx and Rx insertion loss. In this paper, we present a capacitive bridge-based duplexer for full-duplex operation with tunable Tx/Rx insertion loss to improve link budget in an asymmetric data network. Theoretical analysis is done to show that capacitive bridge-based duplexer can be better than hybrid transformer in CMOS process. Capacitive bridge architecture is suitable for insertion loss tunability and this tunability gives an additional advantage of increasing the range of allowed antenna impedance for the given balance network. The fully integrated duplexer with receiver is implemented in a 130-nm CMOS process, and is capable of handling Tx power of upto +16dBm at antenna. The prototype chip demonstrates tunable Tx/Rx insertion loss achieving an overall receiver noise figure of 5.7–7.5dB and a Tx insertion loss of 3.9–5.6dB. Self-interference cancellation of >50dB is measured for 20-MHz RF bandwidth in 2.4–2.6-GHz frequency range.

In this paper, a highly integrated frequency-modulated continuous-wave (FMCW) radar system with a single-antenna interface for range sensing is proposed. In this paper, a circulator structure was developed and used in the radar system with the single-antenna interface. This structure capitalizes on frequency orthogonality to separate transmitted and received signals; thus, the isolation can be improved by using integrated filters to further suppress transmitter leakage. Without an additional back-end leakage cancellation mechanism and antenna tuner, the single-antenna FMCW radar system can be devised. The proposed system is composed of a radar transceiver, a frequency synthesizer, an analog signal processor, and an AD converter; the system is fabricated using a 65-nm CMOS technology, occupies a chip area of 1.9 mm2, and consumes 147-mW dc power under a 1.2-V power supply. The implemented front-end circuit can provide an output power of 10.5 dBm with power efficiency of 30%, over 1-GHz impedance matching, an insertion loss of 2 dB, a maximum noise figure of 16.8 dB (including the following IF amplifier), $P_{1\,\text {dB}}$ of 2 dBm, and IIP3 of 7 dBm. A wireless measurement process proved that the system can provide a 37-cm range resolution over a 50-m range for a $20 \times 20$ cm2 copper plate. Finally, an FMCW radar front-end board and a digital signal processing board were implemented for data analysis, thus completing the FMCW radar sensor unit. The proposed system can be utilized for multiple applications including 1-D object tracking, 2-D localization, and 3-D object tracking.

This paper presents a 680 MHz–6 GHz $2 \times 2$ multiple-input and multiple-output (MIMO) long-term evolution (LTE) RF transceiver in 65-nm CMOS for low-cost and multi-band capable femtocell base stations. The transceiver integrates two receivers (RXs), two transmitters (TXs), and two frequency synthesizers, for the $2 \times 2$ MIMO operation to support both the frequency division duplex (FDD) and the time division duplex (TDD) modes. Each pair of an RX and a TX features eight single-ended low noise amplifiers (LNAs), and eight TX outputs that extensively share active and passive circuits with minimal performance degradation. In the measurement, each RX illustrates the noise figure (NF) from 2.9 to 5.2 dB, the input-referred third-order intercept point (IIP3) of more than −2 dBm, and the IIP2 of more than 48 dBm, over the entire frequency range at the maximum gain. Each TX achieved the adjacent channel leakage ratio (ACLR) that was less than −54 dBc at −5-dBm output power with −157-dBc/Hz phase noise at the RX band, while achieving an error-vector-magnitude (EVM) of less than 2.8%, over the entire frequency range. The transceiver, packaged in a flip-chip chip-scale package (fcCSP), is mounted on the board of the commercial femtocell of the LTE Band5, along with a commercial duplexer, power amplifier, and modem. The femtocell achieved −100-dBm reference sensitivity without the use of an external LNA. It also achieved −51-dBc TX ACLR and 1.68% TX EVM at 20-dBm output power in the LTE 10-MHz mode with the $2 \times 2$ MIMO configuration, without applying a digital pre-distortion (DPD) technique.

This paper proposes a surface-acoustic wave (SAW)-less tunable RF front end (RF-FE) using an electrical-balance duplexer (EBD) integrated with a switched-LC N-path low-noise amplifier (LNA). The EBD cancels the transmitter–receiver (TX–RX) leakage at the RX frequency by dynamically optimizing the balance of a hybrid transformer, which enables in-band full-duplex (IBFD) operation. A transconductor-based LNA in parallel with a switched-LC N-path network creates input and output notches to reject TX leakage for frequency-division duplexing (FDD) operation. The LNA’s signal-handling capability is enhanced via optimum switch biasing. Fabricated in 0.18- $\mu \text{m}$ SOI CMOS, the RF-FE offers >50-dB tunable rejection from the TX port to LNA output at both TX and RX frequencies, for all 3GPP bands from 0.7 to 1 GHz (i.e., FDD case). It is the first tunable RF-FE including an LNA that achieves +70-dBm TX-path IIP3, and +30-dBm in-band TX power while cancelling the self-interference by >50 dB (i.e., IBFD case). The RF-FE consumes 62.5 mW at 1 GHz with 11.7-dB RX cascaded NF, 3.6-dB TX insertion loss, and 9.62 mm2 active area.

A highly linear receiver (RX) front end with integrated hybrid transformer (HT) for frequency-division duplexing mobile communications is reported. The HT, implemented with a three-winding coplanar transformer, is used to interface the RX front end with the antenna and the power amplifier. The primary is driven at its center tap with the transmitted signal and at one input with the antenna signal, while the other input is connected to an on-chip programmable balancing impedance. The two secondary drives a differential push–pull common-gate low-noise amplifier (LNA). Assuming a perfectly linear hybrid only 45 dB of transmitter (TX)–RX isolation and 35 dB of common-mode rejection are required to meet the intermodulation specs thanks to the +25-dBm receiver IIP3. This would drastically simplify hybrid balancing and adaptation loop. Cascaded noise figure of duplexer, LNA, and baseband is below 6.7 dB and TX insertion loss below 4.3 dB from 1.7 to 2.1 GHz. The implemented prototype in 28-nm CMOS has an active area of 0.7 mm2 and requires only 26 mW.

This paper proposes an adaptive RF front-end (RFFE) architecture that uses an electrical-balance duplexer (EBD) and tuned surface acoustic wave (SAW) resonators to enable adaptive dual-frequency isolation suited for LTE’s frequency-division duplex (FDD) mode of operation. Alternatively, in the in-band full-duplex (IBFD) mode, the EBD cancels the in-band TX self-interference directly at RF for increased channel capacity. Furthermore, the EBD’s balance network is optimized to reduce the TX insertion loss (IL) below the nominal 3-dB limit in the FDD mode. A 0.18- $\mu \text{m}$ SOI CMOS prototype implements the EBD, low-noise amplifier, and SAW-tuning capacitor banks. The chip is mounted to a module substrate together with the SAWs and matching components. The RFFE achieves >50-dB dual-frequency isolation and 2.6–3.4-dB TX IL in FDD mode, has +58/+42-dBm TX/RX-path IIP3 for an increased IBFD-link budget and handles up to +27.5-dBm TX power in both modes.

In this paper, two architectures for tunable duplexers are presented. The tuning is accomplished through variable capacitance and resistance. The architectures are based on a three element series-parallel resonator, with one pass and one stop frequency. Both architectures rely on filtering as well as cancellation for good Tx to Rx isolation while maintaining low insertion loss. The first architecture, the filtered transformer balanced (FTB) isolator, has single ended transmit and antenna ports and a differential receive port. The second architecture, the cross coupled filtering (CCF) isolator, is fully differential. For a resonator $Q$ of 50, the impedance ratio of the resonator at pass and stop frequencies is 18.5 dB for 3GPP band-I. In the FTB isolator, this results in 1.65-dB Tx and 2.14-dB Rx insertion loss, and 53 dB isolation for a 20-MHz channel bandwidth. In the CCF isolator, this results in 1.9-dB Tx and 1.9-dB Rx insertion loss, and 59-dB isolation for a 20-MHz channel bandwidth. These figures are obtained with a 20% resistive mismatch, showing feasibility of good performance in an environment with changing impedance. As the operating frequencies of cellular systems increase, these structures will become fully integratable due to the reduced sizes of inductors and transformers.

This paper presents the design consideration on a converged Rx surface acoustic wave (SAW) duplexer module for integrated RF front end. Two different matching-circuit and notch-circuit configurations were examined with importance placed on electrical characteristics (insertion loss and isolation of duplexer) and simplification of module, respectively. From circuit simulations and examinations, we verified that a simplified design was best in terms of both characteristics and space in the case of a finite inductor’s Q. We also fabricate a quad-band converged Rx module (Band I + II, V + VIII) using an SAW duplexer and verified that its electrical characteristics agree well with our simulation results.

Electrical balance duplexers (EBDs) present a potential alternative to the fixed-frequency duplexing filters used for frequency division duplexing in cellular handset radio frequency front ends. However, the transmit-to-receive (Tx–Rx) isolation can be affected by interaction between the antenna and the environment, and therefore, the EBDs balancing impedance must adaptively track time-domain antenna impedance variation. A rail scenario presents a potentially demanding use case for an EBD, as fast moving trains in the vicinity of the antenna may cause dynamically changing reflections, which can be received as self-interference. In this paper, measured dynamic antenna reflection coefficients at 745 and 1900 MHz from train mounted antennas are included in the EBD circuit simulations in order to investigate the resulting variation in Tx–Rx isolation, and determine requirements for balancing impedance adaptation. This paper also presents the results from rail-based field trials of a hardware prototype EBD, which implements real-time antenna impedance tracking. Results show that the rail scenario does result in variation in Tx–Rx isolation, but that rebalancing the EBD at the intervals of 5 ms was sufficient to maintain >50 dB isolation for ~95% of the time.

We present a radio system that could be used in millimeter-scale wireless neural implants. The system is RF-powered and demonstrates Mbps data rates required for neuromodulation and recording applications. The radio transmits at 58 Mb/s and receives at 2.5 Mb/s maximum data rates. The transceiver uses a duplexer to achieve full-duplex communication via frequency-division duplexing at 1.74 and 1.86 GHz for TX and RX, respectively. The average power consumption of the transmitter is 93 $\mu \text{W}$ at 58 Mb/s, while that of the receiver is 7.2 $\mu \text{W}$ at 2.5 Mb/s. The transceiver was fabricated using 40-nm LP CMOS process and occupies 0.8 mm2 of die area. Including the off-chip duplexer, the system occupies 2 $\times $ 1.6 $\times $ 0.6 mm3.

A hybrid transformer-based CMOS tunable duplexer with a single-ended blocker-tolerant low-noise amplifier (LNA) is proposed for a highly integrated reconfigurable RF front-end architecture. The proposed LNA adopts $Q$ -enhanced $LC$ notch filter at the source of the cascode device and $LC$ bandpass filter at the load. It improves the blocker tolerance and linearity of the receiver by rejecting unwanted out-of-band blockers and transmitter (TX) leakage signals. The duplexer with the notch-filtered LNA was fabricated in a 65-nm CMOS process. It has a voltage gain of 24.2 dB from the antenna to the LNA output with 28-dB notch filtering, cascaded noise figure of 6.4 dB, TX insertion loss of 3.8 dB, and IIP3FD of 52.4 dBm. It can also cover a mid-band range from 1.6 to 2.2 GHz in cellular applications. It draws an average current of 8 mA from a supply voltage of 1.2 V and has an active area of 1.19 mm2.

This letter demonstrates a new radio frequency identification (RFID) reader architecture improving the uplink (UL) quality and is compatible with a commercial ultra high frequency Gen2 RFID inlay. The reader transmits a weak auxiliary carrier in addition to the main carrier. The tag nonlinearity generates a new frequency component at the third-order intermodulation (IM3) frequency for UL communication, where the on-tag backscatter works as an on–off-keying modulator at the newly generated IM3 carrier. Since the UL and downlink frequencies are slightly offset, the passives are reused efficiently and the transmitter-to-receiver (Tx-to-Rx) noise/leakage can be eliminated by employing a duplexer, which results in a low-noise and low-interference Rx.

Advances in permanent magnet technology has seen more reports of sensor applications of low field magnetic resonance. Whilst most are either in the 10–20 MHz range or in the earth’s field, measurements at below 1 MHz are beginning to become more widespread. This range is below the need for careful radio frequency electronics design but above the audio domain and represents an interesting cross over. Many commercial spectrometers do not include the pulse power amplifier, duplexer and preamplifier as these depend on the frequency range used. In this work we demonstrate that, with the current specifications of the humble operational amplifier, the most simple form of an inverting design using only two resistors and decoupling, can effectively provide this ‘front end’ electronics. The low powers used mean crossed Ge diodes provide an excellent duplexer and it is suitable for battery powered applications.

Relentless pressure to reduce the size of filters, duplexers and multiplexers in mobile phone RF front end modules requires close packing of the filters and any associated PCB or SMT inductors. In these multiplexers, however, every Tx filter has to reject every Rx frequency and vice versa, while TDD bands/filters must be rejected by and reject nearly every other band -60 dB typical with -55 dB guaranteed. These seemingly contradictory requirements can both be satisfied if we reduce the magnitude of the grounding inductors of the filters to a point that their mutual inductance is not significantly degrading isolation. The Band 25 duplexer described is 1.5 mm x 1.1 mm x 0.6 mm.

This work presents a radio frequency (RF) interface of a full-duplex radio transceiver capable of providing measurements of physical quantities by means of capacitive and inductive sensors incorporated into an oscillator, whose energy supply is harvested from electromagnetic waves sent by a remote central unit. To make this measurement system viable, it makes use of full-duplex communication. This system consists of a duplexer that allows the separation between transmission and reception; of a Colpitts oscillator, whose supply voltage is obtained from a rectifier. This oscillator works both as a measurement system and the RF transmitter, whose carrier frequency is modulated by a measurand providing by a relative humidity sensor. A prototype of this system operating around 27 MHz, simulation and measurement results are also presented.

An electrical-balance duplexer achieving the state-of-the-art linearity and insertion loss (IL) performance is presented, enabled by a partially depleted RF silicon-on-insulator CMOS technology. A single-ended configuration avoids the common-mode isolation problem suffered by topologies with a differential low-noise amplifier. Highly linear switched capacitors allow for impedance balancing to antennas with

This paper proposes a novel concept of an integrated duplex antenna for realizing a compact multifunction RF front end by integrating a duplexer and a dual-band patch antenna. First, an all-resonator-based duplexer is designed. It is composed of two sets of split-ring resonators as channel filters, which are joined by a dual-mode stub-loaded resonator as the junction resonator. Then, a novel dual-band patch antenna is achieved by coupling a patch with a hairpin resonator through a slot in the ground. Uniform radiation characteristics have been achieved across the two bands. Finally, the duplexer is integrated with the dual-band patch antenna to form a highly integrated duplex antenna by coupling the hairpin resonator to the junction resonator of the duplexer directly. In this process, the 50- $\Omega $ interface and matching network between them are removed, contributing to a compact footprint. The details of codesign approach have been discussed in this paper. Compared with the traditional cascaded duplexer and antennas, this paper is much more compact and integrated but with an improved frequency response. A prototype of an integrated duplex antenna at S-band is fabricated and measured, showing two operation channels of 2.52–2.65 GHz for transmitting and 2.82–2.94 GHz for receiving with an isolation of over 32 dB. The measured results agree well with the simulation results.

A tunable integrated electrical balanced duplexer (EBD) is presented as a compact alternative to multiple bulky surface acoustic wave (SAW) and bulk acoustic wave (BAW) duplexers in third-generation (3G)/fourth-generation (4G) cellular transceivers. A balancing network creates a replica of the transmitter (TX) signal for cancellation at the input of a single-ended low-noise amplifier (LNA) to isolate the receive path from the TX. The proposed passive EBD is based on a cross-connected transformer topology without the need of any extra baluns at the antenna side. The balancing network enables a single-ended LNA with reliable high TX power operation up to 22 dBm by alleviating the common-mode coupling. The duplexer achieves around 50-dB transmitter–receiver (TX-RX) isolation within a 1.6–2.2-GHz range. The cascaded noise figure (NF) of the duplexer and LNA is 6.5 dB, and TX insertion loss (TXIL) of the duplexer is about 3.2 dB. The duplexer and LNA are implemented in a ${\hbox{0.18-}}\mu{\hbox{m}}$ CMOS process and occupy an active area of ${\hbox{0.35 mm}}^{2}$ .

A class of frequency-agile planar duplexers with independently controllable channels in terms of center frequency, passband-width, out-of-band power-attenuation characteristics, and tune-all transfer-function capabilities is reported. Each channel filter is made up of frequency-reconfigurable resonators that are coupled to its direct input-to-output electrical path through static impedance inverters and generate power transmission zeros (TZs). Thus, the duplexer channels are exclusively reconfigured by means of dynamic TZ allocation. Furthermore, the channel filters can be intrinsically switched-OFF by incorporating a bandstop-filtering function into them. The operational principles of this spectrally adaptive duplexer concept are expounded and experimentally demonstrated through the manufacturing and characterization of a microstrip prototype in the UHF range.

In this paper, a dual-polarisation shared-aperture duplex antenna is presented for satellite communications at the standard microwave Ku-band, based on the integrated filtering-antenna concept and co-design approach. The design relies on the use of resonators coupled to the radiating dual-band dual-polarisation antenna. The resonant patch antenna forms one pole of each channel filter, resulting in a third-order filter in the Rx channel and a second-order filter in the Tx channel. The Rx and Tx ports of the antenna take in horizontal and vertical linear polarisations, respectively. The integrated duplexer helps to increase the isolation between the ports and the selectivity of each channel. The integration between the filter and the antenna is achieved by electromagnetic coupling, without the need of external matching circuits. Thus it attains a compact footprint. The operation frequencies of the demonstrated duplexantenna are from 11 to 12.5 GHz (12.8%) for the downlink to the Rx port, and from 13 to 14.4 GHz (10.2%) for the uplink at the Tx port. High port-to-port isolation of over 40 dB is realized to reduce channel interference. Flat in-band average gains are achieved to be 8.3 and 8.6 dBi, for the low- and high-bands, respectively.

This paper presents a novel, tunable, frequency-division duplexing radio frequency (RF) front end that combines passive and active self-interference (SI) cancellation. An electrical-balance duplexer is used to passively cancel transmitter noise in the receive band, and an active canceller is employed to suppress SI in the transmit (Tx)-band. Subsystem specifications are developed, and a system-level analysis of noise and SI powers in this novel architecture is provided, thereby illustrating its operation. A proof-of-concept demonstrator, built from a software-defined radio and discrete RF components, has been characterized across a range of duplex configurations in the 700-950-MHz range and also at 1900 (Long-Term Evolution (LTE) band 3) and 2600 MHz (LTE band 7). The prototype achieves an impressive 6.0-7.4-dB noise figure in the presence of a +27-dBm LTE uplink Tx blocker for duplex separations of 47.5 MHz and above. The duplexer has also been tested against reference sensitivity test cases defined in the 3GPP LTE specification, demonstrating specification compliant sensitivity in LTE bands 28 (700 MHz), 3, and 7.

Due to the recent increase of traffic, miniaturization of cellular phone base stations has been strongly expected. Small base stations called Remote Radio Head (RRH) are being installed for advanced small cell. Since the filter duplexer occupies about half of the volume of RRH, miniaturization of the filter is very important. One of the approaches is use of multimode resonator. In this paper, a cavity-type quadrupole-mode resonator with rectangular-shape is investigated. Adjustment mechanisms for resonance frequency and coupling are studied.

Partially depleted silicon-on-insulator (PD-SOI) is a key enabling technology for adaptively tuned RF front-end modules (FEM). Unlike bulk CMOS, thanks to SOI's insulating buried-oxide (BOX) layer, switched capacitor banks can allow for large voltage swing and exhibit a high small-signal linearity. This in turn enables LTE standard-proof power and linearity capabilities for tunable duplexers based on electrical-balance duplexers (EBDs) and N-path filters. These building blocks help to reduce the amount of SAW filters typically required in LTE handsets and enable in-band full-duplex (IBFD). This paper presents an overview of work related to tunable FEM in 180nm PD-SOI technology.

The isolation between transmitter and receiver for the radars is ultimately important since the transmitting radar signals can be penetrated the receiver directly in case a bad isolation is formed. This paper describes the isolation between the transceiver and the design of an integrated full duplexer using the phase locked loop (PLL). Although the antenna impedance varies arbitrarily, the PLL tracks the impedance variation in real time, leading to improvement of isolation between the transmitter and the receiver of radars. The full duplexer reduces the transmitter leakage up to 45 dB using the balance network along with the PLL in measurement.

This paper introduces the design of a broadband switch duplexer. The switch duplexer is used in the microwave measurement instrument. Series-parallel structure of PIN diode is used in the design of switch. Series structure is used in high frequency band, parallel structure is used in low frequency band, and the micro-strip matching circuit is adopted in coupled inductor. Diplexer circuit has many advantages such as low loss, high frequency division point, working at wide-band range, etc.

A low-energy 40/160 MHz dual-band full duplex body channel communication (BCC) transceiver and a 13.56 MHz R-C oscillator-based super-regenerative transceiver are integrated in 65 nm CMOS mixed mode process for both entertainment and healthcare applications. The on-chip R-C duplexer uses notch filters for full duplex communication with 40 Mb/s data rate and combined dual-band operation shows 80 Mb/s data rate with half duplex communication. 40 MHz sine wave and 160 MHz rectangular wave are adopted for modulation in the dual-band transmitter with 30 dB SNR improvement, and shared-loop BPSK receiver reduces the power consumption by 25%. The proposed super-regenerative transceiver including an OOK transmitter and an R-C oscillator-based receiver achieves ${>}60\,\text{dB}$ interference rejection with 100 kb/s data rate and $42.5\,\upmu\text{W}$ power consumption under the 0.8 V supply.

A fully integrated technique for wideband cancellation of transmitter (TX) self-interference (SI) in the RF domain is proposed for multiband frequency-division duplexing (FDD) and full-duplex (FD) wireless applications. Integrated wideband SI cancellation (SIC) in the RF domain is accomplished through: 1) a bank of tunable, reconfigurable second-order high-Q RF bandpass filters in the canceller that emulate the antenna interface’s isolation (essentially frequency-domain equalization in the RF domain) and 2) a linear $N$ -path $G_m$ - $C$ filter implementation with embedded variable attenuation and phase shifting. A 0.8–1.4 GHz receiver (RX) with the proposed wideband SIC circuits is implemented in a 65 nm CMOS process. In measurement, $>20\;\text{MHz}\;20\;\text{dB}$ cancellation bandwidth (BW) is achieved across frequency-selective antenna interfaces: 1) a custom-designed LTE-like 0.780/0.895 GHz duplexer with TX/RX isolation peak magnitude of 30 dB, peak group delay of 11 ns, and 7 dB magnitude variation across the TX band for FDD and 2) a 1.4 GHz antenna pair for FD wireless with TX/RX isolation peak magnitude of 32 dB, peak group delay of 9 ns, and 3 dB magnitude variation over 1.36–1.38 GHz. For FDD, SIC enhances the effective out-of-band (OOB) IIP3 and IIP2 to $+\text{25}\text{-}27\;\text{dBm}$ and $+90\;\text{dBm}$ , respectively (enhancements of 8–10 and 29 dB, respectively). For FD, SIC eliminates RX gain compression for as high as $-8\;\text{dBm}$ of peak in-band (IB) SI, and enhances effective IB IIP3 and IIP2 by 22 and 58 dB.

Carrier aggregation transmissions in frequency division duplexing devices reduce the duplexing distance between the transmitter (TX) and receiver (RX) bands. As a consequence, the spurious intermodulation distortion products created by the nonlinear RF front-end of the TX may easily extend over to the RX band, potentially causing own RX desensitization. In this paper, we propose an efficient and computationally feasible adaptive digital identification and cancellation technique to mitigate the RX desensitization. We first show that the spurious leakage signal at own RX band depends on an equivalent leakage channel that models the overall signal leakage path including the TX nonlinearities, duplexer filter responses, and RX path. The parameters of the equivalent leakage channel can be efficiently estimated with the least squares or the recursive least squares algorithm, using the actual digital transmit data as a reference, and then used to regenerate and cancel the leakage interference from the received signal. The performance of the proposed technique is evaluated with extensive computer simulations, as well as with practical real-world RF measurements, demonstrating excellent calibration properties with up to 19-dB improvement in singal-to-interference plus noise ratio of the desired received signal.

Factors limiting the isolation of conventional miniaturized filters and duplexers have been considered in the literature. They can be classified into two types of signal leakage: one occurs via the main signal path due to the finite impedance of the RX filter in the TX band in a duplexer; the second one is due to electromagnetic feedthrough (EMF), electromagnetic couplings or imperfect grounding. Because of the existence of these leakages, the isolation of usual duplexers is limited to about 50 to 55 dB.

© 2017 IEEE. A 120GHz in-band full-duplex PMF transceiver with tunable electrical-balance duplexer with on-chip antenna is implemented in a 40nm bulk CMOS technology. The self-interference (SI) cancellation is performed with a fully-differential transformer-based electrical-balance duplexer, resulting in a SI suppression of 30dB over a bandwidth of more than 14GHz. The insertion loss of the duplexer is less than 11dB from TX to fiber and less than 12dB from fiber to RX at a frequency of 120GHz. The balancing network impedance can tolerate load impedances from 45Ω to 93Ω and 38fF to 266fF at 120GHz. For in-band full-duplex operation, the maximum measured data rate is 6.2Gbps. The transceiver with integrated antenna occupies an area of 1.8mm × 1.53mm and has a DC power consumption of 73mW in total. ispartof: pages:103-106 ispartof: Proceedings of the ESSCIRC pages:103-106 ispartof: ESSCIRC location:Leuven date:11 Sep - 14 Sep 2017 status: published

A multi-mode multi-band (MMMB) power amplifier module with integrated duplexer (PAMiD) is developed for mobile handset applications. To reduce size and improve RF performance of Tx front-end, the PAMiD consolidates most of the post-PA networks as well as PA block in a single module. This paper summarizes the RF requirements and challenges addressed in recent years that pursue PAMiD development, and discusses its design consideration.

In this paper, a hybrid antenna is proposed for full-duplex system. The antenna design utilizes a single slot for resonance, and the length is 3/4 λ0 for a short circuit at the other port. Therefore, two parallel transmission lines can be extended across the specified slot design and individually connected with two equal length open stubs for impedance matching. After the design optimization, the RF bandwidth is from 24 to 25 GHz, and an isolation 58 dB at the center frequency of the system is achieved by using liquid-crystal polymer (LCP) material for low loss. The front-end module with wire bonding assembly is also considered in 3D simulation. The simulation is performed using transient-solver of CST EM simulation tool, and the meshes of critical structures included the wire bonding, substrate, and slot that will be set to 1/50 step width.

Band 28 has wide bandwidth of 45MHz and narrow duplex gap of 10MHz in 700MHz band, and since digital terrestrial TV channels in some countries are overlapped with lower frequency range of the uplink band, two types of duplexer which have slightly shifted passbands need to be used. This paper describes a novel switchable SAW duplexer which can cover both bands in one duplexer. By using a filter design technique with unique switching circuit, and wideband and low temperature drift SAW resonator technology, high performance such as 2.6/3.0dB insertion loss and 55dB isolation have been achieved, in addition to more than 13/16dB near point attenuation only 5/8MHz apart from the passband edge. The developed switchable duplexer can lead the reduction of 40% in mounting area on RF front-end circuit of mobile terminals.

A 0.7–1GHz tunable front-end module (FEM) is presented for frequency-division duplexing and in-band full-duplex. It combines an electrical-balance duplexer (EBD) and tunable surface-acoustic wave resonators, demonstrating for the first time that these techniques are compatible and can be tuned independently. The EBD is integrated with a low-noise amplifier (LNA) in 0.18μm SOI CMOS and can operate with any antenna with a VSWR less than 2.3:1. The tunable FEM achieves more than 50dB dual-frequency isolation prior to the LNA, 2.6–3.4dB TX insertion loss and +58/+42dBm TX/RX-path out-of-band-IIP 3 , respectively. It has

This paper presents a transformer-less duplexer based on 2-port N-path bandpass filters (BPFs). The proposed duplexer consists of two quarter-wavelength transmission lines, and an N-path balun BPF which provides an out-of-band (OOB) blocker support for the receiver. A 0.45–0.65 GHz duplexer is implemented in a CMOS 65 nm technology. The duplexer occupies an active area of ≈ 0.7 mm2. In post-layout simulations, the duplexer has > 55 dB of transmitter-to-receiver isolation, < 6 dB of transmitter-to-antenna insertion loss (IL) and < 7 dB of antenna-to-receiver IL.

LTE-advanced wireless receivers require high-linearity up-front filtering to prevent corruption of the in-band signals by strong out-of-band (OOB) signals and self-interference from the transmitter. SAW duplexer filters are generally used for this purpose, but supporting the plethora of existing and new bands becomes troublesome with separate filters for each band. In this paper we explore the possibility of combining an isolator with on-chip filtering. However, even with 15dB isolation, the on-chip filter needs to deal with up to +10dBm TX leakage and −15dBm OOB blocking, which requires an extremely high IIP3 around +50dBm and IIP2 around +90dBm. Recently inductorless tunable N-path-filter-based receivers achieved >10dBm compression point and good IIP3 of 20 to 30dBm. In order to further improve the receiver linearity to approach the extremely high IIP3 requirement for a SAW-less receiver, a high-linearity N-path bandpass/notch filter topology and receiver architecture are proposed in this paper.

A balanced RF duplexer with low interference in an extremely narrow bandgap is proposed. The Long-Term Evolution band-7 duplexer should be designed to prevent the co-existence problem with the WiFi band, whose fractional bandgap corresponds to only 0.7%. By implementing a hybrid bulk acoustic wave (BAW) structure, the temperature coefficient of frequency (TCF) value of the duplexer is successfully reduced and the suppressed interference for the narrow bandgap is performed. To achieve an RF duplexer with balanced Rx output topology, we also propose a novel balanced BAW Rx topology and RF circuit block. The novel balanced Rx filter is designed with both lattice- and ladder-type configurations to ensure excellent attenuation. The RF circuit block, which is located between the antenna and the Rx filter, is developed to simultaneously function as a balance-tounbalance transformer and a phase shift network. The size of the fabricated duplexer is as small as . The maximum insertion loss of the duplexer is as low as 2.4 dB in the Tx band, and the minimum attenuation in the WiFi band is as high as 36.8 dB. The TCF value is considerably lowered to .

This letter reports the design and measurements of a SiGe BiCMOS duplexer developed for T/R (transmit/receive) Ka-band SatCom on-the-move user terminals. The IC presented in this work is designed for the integration in a hexa-core chip for dual-band phased array applications. Due to the particular configuration of the chip, the duplexer has four ports: one common port, one input port for the R channel and two output ports for the T channels. The chip size is 570 $\,\times\,$ 400 $\mu$ m $^{2}$ including the measurements pads. Simulated and measured results demonstrate that the proposed device achieves good performance in both frequency bands in terms of input matching, transmission losses and isolation.