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This article presents a low-power, low-distortion, and compact mixed-signal sinusoidal current generator (CG) IC for bio-impedance (Bio-Z) sensing applications. By utilizing the digital ΔΣ modulation to bridge the digitally synthesized sinewave data and the analog-domain voltage output, implementation of a low-distortion sinewave lookup table (LUT) is significantly simplified. Not only does this approach lead to the reduced number of routing wires, pin allocation, and output registers after logic synthesis but also, it allows the use of dynamic element matching (DEM) with a low-cost, before interfacing with the digital-to-analog converter (DAC). In addition, 0.5 V of low-supply voltage exploits a highly power-efficient operation for both synthesized digital logic and its subsequent analog circuit chain. To suppress the noise-floor increase that is induced from the reset signal of capacitor-DAC, a half-period reset scheme is introduced. The prototype chip is fabricated in 65-nm CMOS technology and it outputs 2 μA $_{PP}$ of amplitude with 20 kHz of sinusoidal frequency. It records the first sinusoidal CG IC that achieves sub-10 μW (6.2 μW) of power consumption and sub-0.1% (0.088%) of total harmonic distortion (THD) at the same time which has not been demonstrated ever in the prior arts. Furthermore, 0.059 mm² of its compact area facilitates the low-cost production of Bio-Z sensor systems.

We present an area- and power-efficient application-specific integrated circuit (ASIC) for a miniaturized 3-D ultrasound system. The ASIC is designed to transmit pulse and receive echo through a 36-channel 2-D piezoelectric Micromachined Ultrasound Transducer (pMUT) array. The 36-channel ASIC integrates a transmitter (TX), a receiver (RX), and an analog-to-digital converter (ADC) within the 250- $\mu \text{m}$ pitch channel while consuming low-power and supporting calibration to compensate for the process variation of the pMUT. The charge-recycling high-voltage TX (CRHV-TX) in standard CMOS generates up to 13.2- $\text{V}_{\mathrm {PP}}$ pulse while reducing 42.2% peak TX power consumption. Also, each CRHV-TX automatically calibrates excitation voltage according to acoustic pressure of pMUT. The dynamic-bit-shared ADC (DBS-ADC) shares the most significant bits (MSBs) among four channels based on the signal similarity between adjacent channels. The analog front end (AFE) with a received signal sensitivity indicator (RSSI) changes its gain adaptively in real time depending on input signal strength. The ASIC consumes 1.14-mW/channel average power with 1-kHz pulse repetition frequency (PRF) and three TX pulses per cycle. The ASIC in 0.18- $\mu \text{m}$ 1P6M Standard CMOS has been verified with both electrical and acoustic experiments with a $6\times 6$ pMUT array.

In this article, a body channel communication (BCC) transceiver (TRX) and low-power receiver (RX) that can cover wide applications are proposed. The IEEE 802.15.6 human body communication (HBC) physical layer (PHY) standard and high-speed data transmission are supported simultaneously with a single chip. First, the sinusoidal-modulated transmitter is proposed for the standard mode TRX, and it can reduce filtering power overhead 35%. Second, high-speed TRX is proposed that can support dual-band QPSK modulation to increase system data rate and bandwidth efficiency. Third, on-chip RC duplexer is proposed for full-duplex function in communication. Also, for the low-power RX, a wireless power transfer (WPT)-based wake-up receiver (WuRX) and a higher energy efficiency main RX is integrated into RX chip. The main HBC RX demodulates both ASK and frequency-shift keying (FSK) information with a sharing oscillator (OSC) with 31- $\mu \text{W}$ low-power consumption. The TRX and RX are implemented in 65-nm CMOS process.

In-ear brain–computer interface (BCI) controller system is implemented with a dedicated system-on-chip (SoC) including electroencephalography (EEG) readout and body channel communication (BCC) transceiver (TRX). The 8-mm2 chip is fabricated using 65-nm CMOS and contains three key features: 1) current reusing low-noise amplifier (CRLNA) for low power; 2) bootstrapping dc servo loop (BDSL) enabling low-noise measurement even on 350-mV electrode dc offset (EDO); and 3) dual-mode programmable gain amplifier (DMPGA) that reduces TRX power consumption by activating only when the intentional blink is present. EEG instrumentation amplifier (IA) shows the state-of-the-art 8.8 power efficiency factor (PEF) performance, and the entire integrated circuit (IC) consumes 82.9 $\mu \text{W}$ . From the measurement, with nine subjects, the proposed BCI system accomplished 84% average accuracy for the binary selection task.

This paper presents the first sub-10μW, sub-0.1% THD sinusoidal current generator (CG) IC that is capable of 20kHz output for the bio-impedance (Bio-Z) sensing applications. To benefit from the ultra-low-power nature of near-threshold operation, a 9b pseudo-sine LUT is 3b ΔΣ modulated in the digital domain, thus linearity burden of the DAC is avoided and only a 1.29μW of logic power is consumed, from a 0.5V supply and a 2.56MHz clock frequency. A half-period (HP) reset is introduced in the capacitive DAC, leading to around 30dB reduction of in-band noise by avoiding the sampling of data-dependent glitches and attenuating the kT/C noise and the non-idealities of reset switches (SW).

Autonomous mobile robots are receiving a lot of attention for many applications, such as package delivery and smart surveillance, however, the battery capacity is limited to implement intelligent decision making in robots because of the heavy computational costs. In this paper, an ultra-low-power artificial intelligence processor (AIP) is proposed for real-time decision making of autonomous mobile robots. To achieve low power consumption while maintaining high performance, it adopts four key features: 1) an 8-thread tree search processor for real-time path planning; 2) a reinforcement learning accelerator for the avoidance of unexpected obstacles; 3) a 3-level transposition table cache for the reduction of duplicated computations; and 4) a PVT compensation circuit for the stable operation at near-threshold voltage. The proposed 16 mm $^{{{2}}}$ AIP is fabricated using 65-nm triple-well CMOS technology. It consumes only 1.1 mW at 0.55 V supply voltage and 7 MHz operating frequency, and 151 mW at 1.2 V supply voltage and 245 MHz operating frequency. The AIP achieves fast search speed (470 000 search/s) and low energy consumption (79 nJ/search), and it is successfully applied to a battery-powered robot system for autonomous navigation without any collision in dynamic indoor environments.

A wearable electrical impedance tomography (EIT) system is proposed for the portable real-time 3-D lung ventilation monitoring. It consists of two types of SoCs, active electrode (AE)-SoC and Hub-SoC, mounted on wearable belts. The 48-channel AE-SoCs are integrated on flexible printed circuit board belt, and Hub-SoC is integrated in the hub module which performs data gathering and wireless communication between an external imaging device. To get high accuracy under the variation of conductivity, the dual-mode current stimulator provides the optimal frequency for time difference-EIT and frequency difference-EIT with simultaneous 4 k–128 kHz impedance sensing. A wide dynamic range instruments amplifier is proposed to provide 94 dB of wide dynamic range impedance sensing. In addition, the 48-channel AE system with the dedicated communication and calibration is implemented to achieve 1.4- $\text{m}\Omega $ sensitivity of impedance difference in the in vivo environment. The AE-/Hub-SoCs occupy 3.2 and 1.3 mm2 in 65-nm CMOS technology and consume $124~\mu \text{W}$ and 1.1 mW with 1.2 V supply, respectively. As a result, EIT images are reconstructed with 90% of accuracy, and up to 10 frames/s real-time 3-D lung images are successfully displayed.

A power-efficient human body channel (HBC) RX IC which operates without an external battery is implemented in 65 nm CMOS mixed mode process with 0.6 V supply voltage. The HBC RX IC is designed to receive intermittent data from an external device while generating power by itself. The HBC RX IC integrates an ambient RF energy harvester (EH), a wireless power transfer (WPT)-based wake-up receiver (WuRX), and a low-power main HBC RX. The ambient RF EH harvests standby power of the proposed HBC IC with dynamic input range. The WPT-based WuRX receives incoming wake-up signal and generates power for main HBC RX with 68% power conversion efficiency (PCE) at the same time. The main HBC RX demodulates both ASK and FSK information with the same oscillation with 31 µW low-power consumption. As a result, the proposed HBC RX IC works stand-alone while performing 0.97 µW standby power and 31 µW active power with 0.13nJ/b energy efficiency.

An ultra-low-power duty controlled received signal strength indicator (RSSI) is implemented for human body communication (HBC) in 180 nm CMOS technology under 1.5 V supply. The proposed RSSI adopted 3 following key features for low-power consumption; 1) current reusing technique (CR-RSSI) with replica bias circuit and calibration unit, 2) duty controller, and 3) reconfigurable gm-boosting LNA. The CR-RSSI utilizes stacked amplifier-rectifier-cell (AR-cell) to reuse the supply current of each blocks. As a result, the power consumption becomes 540 $\mu\text{W}$ with +/−2 dB accuracy and 75 dB dynamic range. The replica bias circuit and calibration unit are adopted to increase the reliability of CR-RSSI. In addition, the duty controller turns off the RSSI when it is not required, and this function leads 70% power reduction. At last, the $g_{m}$ -boosting reconfigurable LNA can adaptively vary its noise and linearity performance with respect to input signal strength. Fro current reusing technique m this feature, we achieve 62% power reduction in the LNA. Thanks to these schemes, compared to the previous works, we can save 70% of power in RSSI and LNA.

An ultra-low-power object matching processor is proposed for the autonomous micro air vehicle (MAV) navigation systems. For the ultra-low power consumption, it adopts four low-power features: 1) a 4-point scale-invariant generalized Hough transform (4P-SIGHT) to reduce the computational cost by 51%, 2) a feature streaming pipeline (FSP) to lower the operating frequency by 40%, 3) a Huffman and delta decoder (HDD) to reduce the memory readouts by 35.3%, and 4) a small-area and wide-operating-range 10-transistor level shifter (10T-LS) for the near-threshold voltage (NTV) operation. The proposed 2.0 $\text{mm}^{2}$ object matching processor is fabricated using 65 nm CMOS technology and it consumes only 54 $\mu\text{W}$ at 5 MHz operating frequency and 0.5 V supply voltage while processing QVGA resolution video in 30 fps. It is successfully applied to the MAV and shows 93.5% recognition accuracy for the autonomous navigation. It provides 9.35 $\times$ better energy efficiency than previous state-of-the-art object matching processors.

In this paper, body channel communication and its channel characteristic are investigated through measurement. Previously, the body channel communication has limitation in channel bandwidth due to its fluctuation. To verify orientation, 4 independent systemic factors are under test; (1) the size of the signal electrode attaching on the skin, (2) the size of the ground plane (GND) electrode that is not attaching on the skin, (3) the channel distance between TX and RX through human body, and (4) the length of cable connecting between the transceiver hardware and signal electrode. The size of the electrode and channel communication does not have a high correlation, However, the cable length between electrode and device shows a large variation. The newly proposed results are useful for hardware design and allow larger utilizable channel bandwidth that is promising for future BCC hardware design.

Ultralow-power organic wearable patches have been developed for all-day monitoring of heart rate and blood oxygen level., Pulse oximetry sensors have been playing a key role as devices to monitor elemental yet critical human health states. Conventional pulse oximetry sensors, however, have relatively large power consumption, impeding their use as stand-alone, continuous monitoring systems that can easily be integrated with everyday life. Here, we exploit the design freedom offered by organic technologies to realize a reflective patch-type pulse oximetry sensor with ultralow power consumption. On the basis of flexible organic light-emitting diodes and organic photodiodes designed via an optical simulation of color-sensitive light propagation within human skin, the proposed monolithically integrated organic pulse oximetry sensor heads exhibit successful operation at electrical power as low as 24 μW on average. We thereby demonstrate that organic devices not only have form factor advantages for such applications but also hold great promise as enablers for all-day wearable health monitoring systems.

A low-energy 40/160 MHz dual-band full duplex body channel communication (BCC) transceiver and a 13.56 MHz R-C oscillator-based super-regenerative transceiver are integrated in 65 nm CMOS mixed mode process for both entertainment and healthcare applications. The on-chip R-C duplexer uses notch filters for full duplex communication with 40 Mb/s data rate and combined dual-band operation shows 80 Mb/s data rate with half duplex communication. 40 MHz sine wave and 160 MHz rectangular wave are adopted for modulation in the dual-band transmitter with 30 dB SNR improvement, and shared-loop BPSK receiver reduces the power consumption by 25%. The proposed super-regenerative transceiver including an OOK transmitter and an R-C oscillator-based receiver achieves ${>}60\,\text{dB}$ interference rejection with 100 kb/s data rate and $42.5\,\upmu\text{W}$ power consumption under the 0.8 V supply.

A dedicated ultra-low power fully integrated FSK wake-up receiver (WuRx) for wireless body area network (WBAN) is implemented in 0.18 $\mu$ m CMOS technology with 0.7 V supply voltage. For low power consumption, a body channel communication (BCC) physical layer (PHY) is adopted with an 80 MHz carrier frequency. Moreover, an injection-locking digitally-controlled oscillator (IL-DCO) is used to provide an extraordinary gain and frequency-to-envelope conversion in the simple and power-efficient envelope detection receiver architecture. The IL-DCO plays an important role in amplifying and demodulating the received FSK signal under a tight power budget. Finally, for low system cost without any external components and calibration overhead, a successive approximation register (SAR) auto-calibration algorithm is proposed to promptly calibrate the frequency drift of the IL-DCO. As a result, the fabricated 1 mm $^{{2}}$ single-chip WuRX consumes 45 $\mu$ W with a data rate of 312 kb/s, providing an 80 MHz reference frequency with 0.25% stability within 102 $\mu$ s calibration time. The proposed WuRX delivers a stable reference clock to the main transceiver for crystal-less WBAN applications.

The effects of electrode configuration on body channel communication (BCC) are studied for the development of body channel characteristics, such as frequency response, path loss, and resilience to other interferers. First, this paper introduces nine types of electrode configurations according to the arrangement and direction of both transmitting and receiving electrodes on the body. Each configuration is then modeled by means of vertical and horizontal electric dipoles. From Maxwell’s equations, the complete equations of vertical and horizontal electric fields on the human body, followed by the ratios of the received electric field to the transmitted electric field, are obtained to find the theoretical body channel characteristics and the effect of electrode configurations on the body channel. The theory is verified with measurement results using a network analyzer and balun transformer. In addition to the channel characteristics, the influence of BCC and RF interference on the body channel is investigated and discussed along with receiving electrode configurations. Based on the measurement results, we found that vertical electrodes in the transmitter and horizontal electrodes with longitudinal direction in the receiver is the optimal configuration for BCC in regard to transmission gain, environmental sensitivity, and interference resilience. Finally, we suggest an effective parameter for BCC, which is equivalent reference distance to determine the proper electrode size for the required frequency response. The relation between the parameter and the electrode size is formulated for the purpose of proper electrode utilization in the design of BCC systems as well as in many potential applications.

A mobile electrical impedance tomography (EIT) IC is proposed for early breast cancer detection personally at home. To assemble the entire system into a simple brassiere shape, EIT IC is integrated via a multi-layered fabric circuit board which includes 90 EIT electrodes and two reference electrodes for current stimulation and voltage sensing. The IC supports three operating modes; gain scanning, contact impedance monitoring, and EIT modes for the clear EIT image. A differential sinusoidal current stimulator (DSCS) is proposed for injection of low-distortion programmable current which has harmonics less than $-$ 59 dBc at a load impedance of 2 kΩ. To get high sensitivity, a 6-channel voltage sensing amplifier can adaptively control the gain up to a maximum of 60 dB, and has low input referred noise, 36 nV/ $\surd$ Hz. The 2.5 × 5 mm chip is fabricated in a 0.18 µm 1P6M CMOS process and consumes 53.4 mW on average. As a result, a sensitivity of 4.9 mΩ is achieved which enables the detection of a 5 mm cancer mass within an agar test phantom.

A low-power and high-accuracy current driver IC is proposed for portable electrical impedance tomography (EIT) systems. The proposed IC supports active electrode configuration and has three key features. First, high output impedance current driver is implemented with phase compensation scheme through a delay-locked loop (DLL) to significantly alleviate a phase shift and a required power consumption in the driver. Second, low-power pseudo-sine wave generator is used not only for a low-harmonic distortion but also for a flexible injection frequency utilization. Through the proposed quantization scheme, total harmonic distortion (THD) is reduced by 35%, achieving THD less than 0.5%. Third, the calibration unit is proposed to compensate injection-current amplitude variations among active electrodes. As a result, the proposed current driver IC guarantees more than 1MΩ output impedance over a wide range of injection current up to 400pA and operating frequency from 1kHz to 5MHz, only consuming 2.79mW.

A compact and low-power electro-acupuncture (EA) IC and its Premeasurement System as off-chip board for verification are proposed for medical treatment and experiment. The multi-mode stimulator EA IC can perform adaptive charge balancing with various load condition as well as programmable supply voltage for 5 different stimulation modes. The proposed EA IC occupies 2.2 mm × 1.5 mm including pads manufactured through 0.11 µm 1P6M CMOS technology and dissipates 1.8 mW at 1.2 V supply supporting 256 different current level with >1G output impedance. The Premeasurement System with corresponding specification to the proposed fabricated EA IC is fully implemented and tested on the human body and animal.

This paper presents a low power, high resolution bio-impedance sensor IC for respiration monitoring application. It contains the dual path instrumentation amplifier (DPIA) including current reusing transconductance amplifier and high gain transimpedance amplifier for high resolution, low power and wide input range bio-impedance measurement. Measured results show that the proposed readout circuit has 354 nV rms input noise and 2.12 μW of the lowest power consumption along with the widest differential input range of 52 mV pp as well. As a result, the readout circuit enables bio-impedance sensor IC to uphold a comparable 38.51 mΩ rms impedance resolution with a relatively smaller 26 μA pp injection current than previous works. This leads to a 24 μW of lowest overall power consumption of bio-impedance sensor. In this sense, the proposed bio-impedance sensor IC achieves its figure of merit (FoM) by value that is 4 times lower compared to the state-of-the-art.

An ultra-low power wake-up receiver for body channel communication (BCC) is implemented in 130 nm CMOS process. The proposed wake-up receiver uses the injection-locking ring oscillator (ILRO) to replace the RF amplifier with low power consumption. Through the ILRO, the frequency modulated input signal is amplified to the full swing rectangular signal directly demodulated by the following low power PLL-based FSK demodulator. In addition, the energy-efficient BCC link mitigates the sensitivity and selectivity requirements for the receiver, which significantly reduces the power consumption. Furthermore, the auto frequency calibrator (AFC) is adopted to compensate the free running frequency of the ring oscillator which is caused by temperature variation and leakage current. The AFC reuses the PLL-based demodulator to periodically set the free running frequency to the desired frequency without any area overhead. As a result, the proposed wake-up receiver achieves a sensitivity of -62.7 dBm at a data rate of 200 kbps while consuming only 37.5 μW from the 0.7 V supply.

In this article, we give an overview of these items and discuss the associated technological trends. In the first section, the history of wearable electronics is summarized, with special emphasis on I/O systems and substrate and packaging issues. Interconnections for wearable devices are introduced in the second section; they can be split into wireline and wireless approaches, as well as permanent versus detachable connections. In the third section, wearable health care systems on a chip (SoCs) and systems on textiles (SoTs) are explained in connection with their appropriate applications. Since wearable health care applications are a good match with wearable technologies, most of the dedicated chips have been developed for health care monitoring, diagnosis, and treatment. A final section presents anumber of conclusions regarding wearable electronics.

A low-power non-contact compensation IC for body channel communication (BCC) is proposed. The proposed IC has 3 key building blocks. First, a contact status detection unit (CSDU) based on a capacitance sensor is adopted. Second, non-contact compensation unit (NCU) with inductor and capacitance bank is proposed. Third, a reconfigurable low noise amplifier (LNA) for impedance matching is adopted. The input impedance of the LNA is controlled by a digital controller for high Q compensation. Thanks to the proposed features, 14 dB channel compensation is achieved and the IC consumed only 635 μW in 65 nm CMOS technology with 1.2 V supply. The proposed work is the first BCC IC with non-contact compensation.

A dedicated ultra-low power arterial pulse wave (APW) sensor for wrist watch type system is implemented in 0.18-μm CMOS technology with 1.8-V supply. A duty cycle controlled (DCC) current source (CS) enables low-power consuming current injection with 98% power reduction. A DC balanced amplifier reduces settling time by 72%, enabling fast APW signal acquisition when motion artifact is occurred. The simulated 2.125-mm2 single chip APW sensor consumes only 54-μW.

A compact electro-acupuncture (EA) system is proposed for a multi-modal feedback EA treatment. It is composed of a needle, a compact EA patch, and an interconnecting conductive thread. The 3 cm diameter compact EA patch is implemented with an adaptive stimulator IC and a small coin battery on the planar-fashionable circuit board (P-FCB) technology. The adaptive stimulator IC can form a closed current loop for even a single needle, and measure the electromyography (EMG) and the skin temperature to analyze the stimulation status as well as supply programmable stimulation current (40 μA-1 mA) with 5 different modes. The large time constant (LTC) sample and hold (S/H) current matching technique achieves the high-precision charge balancing (;10 nA) for the patient's safety. The measured data can be wirelessly transmitted to the external EA analyzer through the body channel communication (BCC) transceiver for the low power consumption. The external EA analyzer can show the patient's status, such as the muscle fatigue and the change of the skin temperature. Based on these analyses, the practitioner can adaptively change the stimulation parameters for the optimal treatment value. A 12.5 mm(2) 0.13 μm RF CMOS stimulator chip consumes 6.8 mW at 1.2 V supporting 32 different current levels. The proposed compact EA system is fully implemented and tested on the human body.

An energy-efficient 920 MHz FSK transceiver for wireless body sensor network (BSN) applications is implemented in 0.18 μm CMOS technology with 0.7 V supply. A transceiver architecture based on injection-locked frequency divider (ILFD) is proposed for the low energy consumption. In the receiver, the ILFD in the signal path converts the received FSK signal to amplitude-modulated signal which is applied to the next envelope detector. In the transmitter, the ILFD is used as digitally-controlled oscillator (DCO) which directly modulates the FSK signal with digital data. The DCO replaces the frequency synthesizer to eliminate the crystal oscillator (XO), which leads to reduce power consumption and cost. The transceiver can detect whether injection locking occurs or not, and calibrates the frequency drift of DCO over temperature variation thanks to ILFD based architecture. The receiver and transmitter consume 420 μW and 700 μW , respectively, at - 10 dBm output power with a data rate of 5 Mb/s, corresponding to energy consumption of 84 pJ per received bit and 140 pJ per transmitted bit.

A low power highly sensitive Thoracic Impedance Variance (TIV) and Electrocardiogram (ECG) monitoring SoC is designed and implemented into a poultice-like plaster sensor for wearable cardiac monitoring. 0.1 Ω TIV detection is possible with a sensitivity of 3.17 V/Ω and SNR > 40 dB. This is achieved with the help of a high quality (Q-factor > 30) balanced sinusoidal current source and low noise reconfigurable readout electronics. A cm-range 13.56 MHz fabric inductor coupling is adopted to start/stop the SoC remotely. Moreover, a 5% duty-cycled Body Channel Communication (BCC) is exploited for 0.2 nJ/b 1 Mbps energy efficient external data communication. The proposed SoC occupies 5 mm × 5 mm including pads in a standard 0.18 μm 1P6M CMOS technology. It dissipates a peak power of 3.9 mW when operating in body channel receiver mode, and consumes 2.4 mW when operating in TIV and ECG detection mode. The SoC is integrated on a 15 cm × 15 cm fabric circuit board together with a flexible battery to form a compact wearable sensor. With 25 adhesive screen-printed fabric electrodes, detection of TIV and ECG at 16 different sites of the heart is possible, allowing optimal detection sites to be configured to accommodate different user dependencies.

Fabrication methods of planar printed circuits on fabrics are introduced and their electrical characteristics are measured and analyzed. Wet patterning method like screen printing as well as dry process of sputtering are used to fabricate the patterned film electrodes on various types of fabrics. The minimum width of the patterns is 0.2 mm for screen printing and 0.1 mm for gold sputtering, and the typical sheet resistance is 134 m ?/?. Fabrication methods of capacitors of 1 pF-1 nF and inductors of 500 nH-1 ?H at 10 MHz on the fabrics are also introduced. Bonding and packaging of silicon chip directly on the fabric circuit board are proposed and their mechanical properties are investigated. The ac impedance of the transmission line is measured as 201-215 ? with variation, and the time-domain reflectometry profile shows that the -3 dB frequency of the printed transmission line of 15 cm on the fabric is 80 MHz. A complete system composed of a fabric capacitor sensor input, a controller system-on-a-chip, and an LED array display is implemented on the fabric and its operation is demonstrated successfully.

A self-configured body sensor network controller and a high efficiency wirelessly powered sensor are presented for a wearable, continuous health monitoring system. The sensor chip harvests its power from the surrounding health monitoring band using an Adaptive Threshold Rectifier (ATR) with 54.9% efficiency, and it consumes 12 μW to implement an electrocardiogram (ECG) analog front-end and an ADC. The ATR is implemented with a standard CMOS process for low cost. The adhesive bandage type sensor patch is composed of the sensor chip, a Planar-Fashionable Circuit Board (P-FCB) inductor, and a pair of dry P-FCB electrodes. The dry P-FCB electrodes enable long term monitoring without skin irritation. The network controller automatically locates the sensor position, configures the sensor type (self-configuration), wirelessly provides power to the configured sensors, and transacts data with only the selected sensors while dissipating 5.2 mW at a single 1.8 V supply. Both the sensor and the health monitoring band are implemented using P-FCB for enhanced wearability and for lower production cost. The sensor chip and the network controller chip occupy 4.8 mm2 and 15.0 mm2, respectively, including pads, in standard 0.18 μm 1P6M CMOS technology.

A Real-time Capacitor Compensation (RCC) scheme is proposed for low power and continuous communication in the wearable inductive coupling transceiver. Since inductance values of wearable inductor vary dynamically with deterioration of its communication characteristics, the inductance value is monitored and its resonance frequency is adjusted by additive parallel/serial capacitors in real time. RLC Bridge for detection of the inductance variations and the Dual-edge Sampling Comparator for recognition of the variance direction are proposed. It is implemented in a 0.18µm CMOS technology, and it occupies a 1 × 2.7mm2 chip area. The proposed transceiver consumes only 426.6µW at 4Mbps data rate. The compensation time takes 4.78µs, including 3µs of detection and 1.78µs for compensation process in worst case.

With the increasing number of portable and implantable personal health care devices, there is a strong demand to control their communication in a single wireless network. Recently, the IEEE 802.15 WBAN task group has discussed the combining of wearable and implantable body sensor networks (BSNs) [1], but no real chip implementation has been reported. In this paper, the implementation of a unified BSN as shown in Fig. 24.9.1 is described.. The unified BSN combines low-power body-channel communication (BCC) [2] and versatile medical implant communication service (MICS) [3] using a network controller located on the human body. This unified BSN has 2 main advantages over the conventional BSNs. First, the MICS band antenna shared with the BCC electrode can be attached directly to human skin to shorten the communication distances among the controller and implanted radios, relaxing their sensitivity and selectivity requirements. Second, due to low path loss of the human body channel, low-power communication is possible among the wearable devices [4]. In addition, the on-body sensors do not need external antennas because the bio-signal sensing electrode functions as the interface for data transmission.

A near-field coupling transceiver integrated with a fault-tolerant network switch is implemented for inter-layer and intra-layer wearable body area network. The inductive coupling transceiver employs a resonance compensator (RC) with a digitally controlled on-chip capacitor bank and a variable hysteresis Schmitt trigger to compensate dynamic and static variances of woven inductor, and it enables 10 Mbps wireless transaction with the reception energy of 1.12 pJ/b at 2.5 V supply. The network switch introduces new fault-tolerant protocol to eliminate the routing table and reduces power consumption by 70% compared with the conventional switch using torus topology. The transceiver with the switch and the RC are implemented in 0.25-mum 1P5M CMOS process technology, occupying 2.0 mm2 and 0.8 mm2 area, respectively.

A 2.5 times 1.8 cm2 medical implant communication service band antenna is combined with an electrode for body channel communication. The proposed design enables a body sensor network controller to communicate with health-care devices located on and inside a patient's body. The spiral microstrip antenna with its radiating body and ground plane placed side-by-side has the thickness of 2 mm and can be attached to human skin conveniently. The propagation loss of the body channel is measured when the proposed antenna is used as the skin interface for BCC in the 10-70-MHz band, and the results are compared with the cases of Ag/AgCl and circular dry electrodes. The equivalent-circuit model of the antenna as the electrode is also derived from the measured impedance characteristics. The LC resonance structure to drive the on-body antenna with its capacitance increased due to the skin contact reduces the power consumption of the TX buffer by >50%. TheS 11-parameter of the on-body antenna, its radiation pattern, and the signal loss inside the human body are investigated.

A new flexible electronics technology, named P-FCB (Planar Fashionable Circuit Board), is introduced. P-FCB is a circuit board technology implemented on the plain fabric patch for wearable electronics applications. In this paper, the manufacturing of PFCB, and its electrical characteristics such as sheet resistance, maximum current density, and frequency characteristics are reported. The fabrication methods and their electrical characteristics of passive devices such as resistor, capacitor, and inductor in P-FCB are discussed. In addition, how to integrate silicon chip directly to the fabric for the flexible electronics system are described. Finally, examples of P-FCB applications will be presented.

A 200-Mbps 0.02-nJ/b dual-mode inductive coupling transceiver is proposed for cm-range multimedia application. The inductive link geometry and the advantage of the pulse-based inductive coupling are explained. In this paper, the parallel capacitor connected with the TX inductor, the intersymbol interference (ISI) reduction scheme, and the pulse generation scheme are newly proposed. The parallel capacitor connected with the TX inductor increases the transmitter impedance so that it enhances the transmission distance by twofold, and the ISI reduction scheme pushes data rate up to 200 Mbps. Moreover, the pulse generation scheme reduces the energy consumption as low as 0.02 nJ/b. Maximum data rate and energy consumption are achieved in simulation. The transceiver occupies 0.012 mm2 in 0.25-mum CMOS process.

An interference-resilient 60 kb/s-10 Mb/s body channel transceiver using the human body as a signal transmission medium is designed for multimedia and medical data transaction in body-area network. The body antenna effect which interferes with signals in the human body channel is examined. The body-induced interferences degrade the SIR of the signal to -22 dB in the worst case. In order to overcome the body antenna effect, a 4-channel adaptive frequency hopping scheme using the 30-120 MHz band is introduced to the body channel transceiver. A direct-switching modulator using dual frequency synthesizers and a DLL-based demodulator are proposed for 10 Mb/s FSK and the 4.2 mus hopping time. The transceiver fabricated with 0.18 mum CMOS withstands -28 dB SIR and its operating distance is over 1.8 m with - 25 dB SIR. Its energy consumption is 0.37 nJ/b with -65 dBm sensitivity.

This paper presents a low-power wideband signaling (WBS) digital transceiver for data transmission through a human body for body area network applications. The low-power and highspeed human body communication (HBC) utilizes a digital transceiver chip based on WBS and adopts a direct-coupled interface (DCI) which uses an electrode of 50-Omega impedance. The channel investigation with the DCI identities an optimum channel bandwidth of 10 kHz to 100 MHz. The WBS digital transceiver exploits a direct digital transmitter and an all-digital clock and data recovery (CDR) circuit. To further reduce power consumption, the proposed CDR circuit incorporates a low-voltage digitally-controlled oscillator and a quadratic sampling technique. The WBS digital transceiver chip with a 0.25-mum standard CMOS technology has 2-Mb/s data rate at a bit error rate of 1.1 times 10-7, dissipating only 0.2 mW from a 1-V supply generated by a 1.5-V battery.

A low-energy 40MHz / 160MHz dual band full duplex body channel communication (BCC) transceiver and 13.56MHz R-C oscillator-based super-regenerative receiver are integrated in 65nm mixed mode CMOS process for both highspeed (HS) and low-speed (LS) biomedical applications. The body channel bandwidth is extended up to 200MHz, enabling energy efficient and wide bandwidth communication. The on-chip R-C duplexer uses notch filters for full duplex communication with 40Mb/s data rate and combined dual band operation shows 80Mb/s data-rate with half duplex communication. The R-C oscillator-based super-regenerative receiver achieves >60dB interference rejection (Q-factor over 1000) with 100kb/s data rate and 42.5μW power consumption under 0.8V supply.

Lung ventilation monitoring electrical impedance tomography (EIT) SoC is implemented in 0.18μm CMOS technology. A dual frequency division multiplexing (DFDM) method is proposed to extract accurate lung ventilation. To realize the DFDM, the proposed EIT SoC adopts a dual frequency current generator (DFCG) and a dual frequency read-out front-end (DFRF) to process the two frequencies in one channel at once. Consequently, 65.1% of power consumption and 71.5% of area are reduced in each channel. In the DFCG, dynamic element matching (DEM) and adaptive quantization (AQ) techniques are adopted to achieve −46dBc total harmonic distortion. In the DFRF, a weaver demodulator (WD) and a trimmed notch filter combined with low-pass filter (TN-LPF) reduce the settling time of the sensor front-end by 83.3% (0.17ms) to achieve the 30fps real-time operation with 32 electrodes. The proposed EIT SoC is successfully verified by both in-vitro and in-vivo test and achieved 95.35% accuracy.

A low power adaptive controlled current-reusing received signal strength indicator (RSSI) is proposed for the human body communication (HBC). The proposed RSSI has three low power features. First, the power on controller (PoC) scheme is proposed to achieve the duty control of the RSSI. It significantly reduces the average power consumption of RSSI over 90%. Second, the current stacking scheme is adopted to share both eight rectifiers and eight amplifiers, composing the RSSI. By the current reusing technique, the power consumption of the RSSI is reduced to 45%. In addition, the reconfigurable LNA is used in the front-end of HBC TRX. The RSSI adaptively controls the gain and noise figure of the LNA to optimize the power consumption. The proposed RSSI occupies 0.85mm2 in 0.18-μm CMOS technology.

An active solution is proposed to overcome the uncertainty and fluctuation of the device parameters in nanotechnology SRAM. The proposed scheme is composed of sensing blocks, analysis blocks and control blocks. An on-chip timer, temperature sensor, substrate noise detector, and leakage current monitor are used to monitor internal status of chip during operation. From the sensed data, internal supply voltage, internal timing margin from decoding to sensing time, substrate noise from digital area, and low voltage level of wordline are controlled. A 512-kb test SRAM chip, fabricated with an 80-nm double stacked cell technology, shows that average power consumption is reduced by 9% and the standard deviation decreases by 58%.

A regulated charge pump circuit is realized in a 3.3-V 0.13-/spl mu/m CMOS technology. The charge pump exploits an automatic pumping control scheme to provide small ripple output voltage and fast start-up by decoupling output ripple and start-up time. The automatic pumping control scheme is composed of two schemes, an automatic pumping current control scheme and an automatic pumping frequency control scheme. The former automatically adjusts the size of pumping driver to reduce ripple voltage according to output voltage. The latter changes the pumping period by controlling a voltage-controlled oscillator (VCO). The output frequency of the VCO varies from 400 kHz to 600 kHz by controlling the input bias voltage of the VCO. The prototype chip delivers regulated 4.5-V output voltage from a supply voltage of 3.3 V with a flying capacitor of 330 nF, while providing 30 mA of load current. The area is 0.25 mm/sup 2/ and the measured output ripple voltage is less than 33.8 mV with a 2-/spl mu/F load capacitor. The power efficiency is greater than 70% at the range of load current from 1 to 30 mA. An analytical model for ripple voltage and recovery time is proposed demonstrating a reasonable agreement with SPICE simulation results.

A 1-Gb/s differential transimpedance amplifier (TIA) is realized in a 0.25-/spl mu/m standard CMOS technology, incorporating the regulated cascode input configuration. The TIA chip is then integrated with a p-i-n photodiode on an oxidized phosphorous-silicon (OPS) substrate by employing the multichip-on-oxide (MCO) technology. The MCO TIA demonstrates 80-dB/spl Omega/ transimpedance gain, 670-MHz bandwidth for 1-pF photodiode capacitance, 0.54-/spl mu/A average input noise current, -17-dBm sensitivity for 10/sup -12/ bit-error rate (BER), and 27-mW power dissipation from a single 2.5-V supply. It also shows negligible switching noise effect from an embedded VCO on the OPS substrate. Furthermore, a four-channel MCO TIA array is implemented for optical interconnects, resulting in less than -40-dB crosstalk between adjacent channels.

A transimpedance amplifier (TIA) has been realized in a 0.6-/spl mu/m digital CMOS technology for Gigabit Ethernet applications. The amplifier exploits the regulated cascode (RGC) configuration as the input stage, thus achieving as large effective input transconductance as that of Si Bipolar or GaAs MESFET. The RGC input configuration isolates the input parasitic capacitance including photodiode capacitance from the bandwidth determination better than common-gate TIA. Test chips were electrically measured on a FR-4 PC board, demonstrating transimpedance gain of 58 dB/spl Omega/ and -3-dB bandwidth of 950 MHz for 0.5-pF photodiode capacitance. Even with 1-pF photodiode capacitance, the measured bandwidth exhibits only 90-MHz difference, confirming the mechanism of the RGC configuration. In addition, the noise measurements show average noise current spectral density of 6.3 pA//spl radic/(Hz) and sensitivity of -20-dBm for a bit-error rate of 10/sup -12/. The chip core dissipates 85 mW from a single 5-V supply.

This special issue brings together 11 papers on approaches spanning circuits, architectures, algorithms, and system design that demonstrates promising solutions to emerging critical problems in body sensor networks.

An electrical impedance tomography (EIT) SoC is proposed for the portable real-time lung ventilation monitoring system. The proposed EIT SoC is integrated into belt-typefabric system with 32 electrodes and can show the dynamic images of the lung ventilation on the mobile devices. To get high fidelity images, a T-switch is adopted for high off-isolation between electrodes more than 60 dB, and I/Q signal generation and demodulation can obtain both real and imaginary part of images. For the real-time imaging, an on-chip fast demodulation scheme is proposed, and it can also reduce speed requirements of ADC for low-power consumption. The proposed EIT SoC of 5.0 mm × 5.0 mm is fabricated in 0.18 µm CMOS technology, and consumes only 10.4 mW with 1.8 V supply. As a result, EIT images were reconstructed with 97.3% of accuracy and up to 20 frames/s real-time lung images can be displayed on the mobile devices.

Semiconductor systems connected through wireless and wired networks are the mainstream approach in the semiconductor market to achieve technical innovations and business advantages. Systems are defined differently according to the application area, implementation technology and also the individual engineer's background. This presents challenges to circuit designers and circuit-design educators.