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A microaccelerometer with highly reliable, wafer-level packaged MEMS sensing element and fully differential, continuous time, low noise, BiCMOS interface circuit is fabricated. The MEMS sensing element is fabricated on a (111)-oriented SOI wafer by using the SBM (Sacrificial/Bulk Micromachining) process. To protect the silicon structure of the sensing element and enhance the reliability, a wafer level hermetic packaging process is performed by using a silicon-glass anodic bonding process. The interface circuit is fabricated using 0.8 µm BiCMOS process. The capacitance change of the MEMS sensing element is amplified by the continuous-time, fully-differential transconductance input amplifier. A chopper-stabilization architecture is adopted to reduce low-frequency noise including 1/f noise. The fabricated microaccelerometer has the total noise equivalent acceleration of 0.89 µg/√Hz, the bias instability of 490 µg, the input range of ±10 g, and the output nonlinearity of ±0.5 %FSO.

A novel CMOS LC oscillator architecture combining an LC tuned oscillator and a ring structure is presented as a new design topology to deliver improved phase noise for multiphase applications. The relative enhancement in the phase noise is estimated using a linear noise modeling approach. A three-stage LC-ring oscillator fabricated in a 0.6 mm CMOS technology achieves measured phase noise of -132 dBc/Hz at 600 kHz offset from a 900 MHz carrier and dissipates 20 mW with a 2.5 V power supply.

A two chip implemented, wafer-level hermetically packaged accelerometer is presented. The accelerometer core is fabricated using the SBM (sacrificial bulk micromachining) process. The fabricated accelerometer core accomplishes high performance, high yield and high reliability by the inherent high-aspect-ratio, footing-free advantages of the SBM process. In order to protect the accelerometer core from environmental changes, a wafer-level hermetic packaging process is performed by using glass-silicon anodic bonding. The capacitive detection circuit adopts an EEPROM trimmable architecture to reduce the die-to-die variations. The fabricated accelerometer has the noise equivalent acceleration resolution of 43 /spl mu/g, input range of /spl plusmn/10 g, Output nonlinearity of 0.1% FSO, scale factor of 130 mV/g, and 4-hr bias stability of 1.10 mg.