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The reliability of grid-connected inverters can be improved by algorithms capable of diagnosing faults in LCL filters. A fault diagnostic method during inverter startup is proposed. The proposed method can accurately generate and monitor information on the peak value and the location of the peak frequency component of the step response of a damped LCL filter. To identify faults, the proposed method compares the evaluated response with the response of a healthy higher-order damped LCL filter. The frequency components in the filter voltage response are first analytically obtained in closed form, which yields the expected trends for the filter faults. In the converter controller, the frequency components in the filter voltage response are computed using an appropriately designed fast Fourier transform and compared with healthy LCL response parameters using a finite state machine, which is used to sequence the proposed startup diagnostics. The performance of the proposed method is validated by comparing analytical results with the simulation and experimental results for a three-phase grid-connected inverter with a damped LCL filter.

Insulated gate bipolar transistors (IGBT) have evolved significantly and become exceedingly fast. Today, their typical switching speeds are of the order of 100 ns. The resulting dv/dt is considerably large and when employed in a variable speed motor drive inverter, ringing over-voltages occur at the motor terminals even with cable as short as 1 meter in length. In any such power converter system, protection of IGBT in the event of a fault is an essential requirement. An effective way of protection is by detecting IGBT de-saturation, which occurs during device over-current or short-circuit, using sensed collector-emitter voltage (V-CE). Several commercial isolated gate-driver ICs are available today in the market with integrated V-CE de-saturation protection feature. Such a protection scheme when employed in a modern IGBT based power converter and used for motor drive applications can lead to spurious trips. This paper investigates and reports the reasons for such spurious fault sensing by IGBT gate-drivers employed in two-level inverters. The circuit conditions are analyzed and it is shown that the IGBTs essentially act as capacitors while switching low currents. This behavior in combination with other factors such as fast device switching times, load power factor, and dead-time, is shown to cause spurious V-CE fault trips. Two simple and cost-effective circuit modifications are suggested which ensure that such spurious fault sensing is avoided in power converters.

Grid-interactive power converters are normally synchronized to the grid using phase-locked loops (PLLs). The performance of the PLLs is affected by the non-ideal conditions in the sensed grid voltage such as harmonics, frequency deviations and dc offsets in single-phase systems. In this paper, a single-phase PLL is presented to mitigate the effects of these non-idealities. This PLL is based on the popular second order generalized integrator (SOGI) structure. The SOGI structure is modified to eliminate of the effects of input dc offsets. The resulting SOGI structure has a high-pass filtering property. Hence, this PLL is termed as high-pass generalized integrator based PLL (HGI-PLL). It has fixed parameters which reduces the implementation complexity and aids in the implementation in low-end digital controllers. The HGI-PLL is shown to have least resource utilization among the SOGI based PLLs with dc cancelling capability. Systematic design methods are evolved leading to the design that limits the unit vector THD to within 1% for given non-ideal input conditions in terms of frequency deviation and harmonic distortion. The proposed designs achieve the fastest transient response. The performance of this PLL has been verified experimentally. The results are found to agree with the theoretical prediction., Comment: 22 pages, 13 figures and 2 tables

Closed loop current sensors used in power electronics applications are expected to have high bandwidth and minimal measurement transients. In this paper, a closed loop compensated Hall-effect current sensor is modeled. The model is used to tune the sensor's compensator. Analytical expression of step response is used to evaluate the performance of the PI compensator in the current sensor. This analysis is used to devise a procedure to design parameters of the PI compensator for fast dynamic response and for small dynamic error. A prototype current sensor is built in the laboratory. Simulations using the model are compared with experimental results to validate the model and to study the variation in performance with compensator parameters. The performance of the designed PI compensator for the sensor is compared with a commercial current sensor. The measured bandwidth of the designed current sensor is above 200 kHz, which is comparable to commercial standards. Implementation issues of PI compensator using operational amplifiers are also addressed.

This paper presents the design of a start up power circuit for a control power supply (CPS) which feeds power to the sub-systems of High Power Converters (HPC). The sub-systems such as gate drive card, annunciation card, protection and delay card etc; needs to be provided power for the operation of a HPC. The control power supply (CPS) is designed to operate over a wide range of input voltage from 90Vac to 270Vac. The CPS output supplies power at a desired voltage of Vout =24V to the auxiliary sub-systems of the HPC. During the starting, the power supply to the control circuitry of CPS in turn, is obtained using a separate start-up power supply. This paper discusses the various design issues of the start-up power circuit to ensure that start-up and shut down of the CPS occurs reliably. The CPS also maintains the power factor close to unity and low total harmonic distortion in input current. The paper also provides design details of gate drive circuits employed for the CPS as well as the design of on-board power supply for the CPS. Index terms: control power supply, start-up power supply, DSFC, pre-regulator

Power semiconductor devices have finite turn on and turn off delays that may not be perfectly matched. In a leg of a voltage source converter, the simultaneous turn on of one device and the turn off of the complementary device will cause a DC bus shoot through, if the turn off delay is larger than the turn on delay time. To avoid this situation it is common practice to blank the two complementary devices in a leg for a small duration of time while switching, which is called dead time. This paper proposes a logic circuit for digital implementation required to control the complementary devices of a leg independently and at the same time preventing cross conduction of devices in a leg, and while providing accurate and stable dead time. This implementation is based on the concept of finite state machines. This circuit can also block improper PWM pulses to semiconductor switches and filters small pulses notches below a threshold time width as the narrow pulses do not provide any significant contribution to average pole voltage, but leads to increased switching loss. This proposed dead time logic has been implemented in a CPLD and is implemented in a protection and delay card for 3- power converters.

Gate driver is an integral part of every power converter, drives the power semiconductor devices and also provides protection for the switches against short-circuit events and over-voltages during shut down. Gate drive card for IGBTs and MOSFETs with basic features can be designed easily by making use of discrete electronic components. Gate driver ICs provides attractive features in a single package, which improves reliability and reduces effort of design engineers. Either case needs one or more isolated power supplies to drive each power semiconductor devices and provide isolation to the control circuitry from the power circuit. The primary emphasis is then to provide simplified and compact isolated power supplies to the gate drive card with the requisite isolation strength and which consumes less space, and for providing thermal protection to the power semiconductor modules for 3-� 3 wire or 4 wire inverters.

High frequency PWM inverters produce an output voltage spectrum at the fundamental reference frequency and around the switching frequency. Thus ideally PWM inverters do not introduce any significant lower order harmonics. However, in real systems, due to dead-time effect, device drops and other non-idealities lower order harmonics are present. In order to attenuate these lower order harmonics and hence to improve the quality of output current, this paper presents an \emph{adaptive harmonic elimination technique}. This technique uses an adaptive filter to estimate a particular harmonic that is to be attenuated and generates a voltage reference which will be added to the voltage reference produced by the current control loop of the inverter. This would have an effect of cancelling the voltage that was producing the particular harmonic. The effectiveness and the limitations of the technique are verified experimentally in a single phase PWM inverter in stand-alone as well as g rid interactive modes of operation.

High power converters are used in variable speed induction motor drive applications. Riding through a short term power supply glitch is becoming an important requirement in these power converters. The power converter uses a large number of control circuit boards for its operation. The control power supply need to ensure that any glitch in the grid side does not affect any of these control circuit boards. A power supply failure of these control cards results in shut down of the entire system. The paper discusses the ride through system developed to overcome voltage sags and short duration outages at the power supply terminals of the control cards in these converters. A 240VA non-isolated, bi-directional buck-boost converter has been designed to be used along with a stack of ultracapacitors to achieve the same. A micro-controller based digital control platform made use of to achieve the control objective. The design of the ultracapacitor stack and the bidirectional converter is described the performance of the experimental set-up is evaluated.

Grid-connected systems when put to use at the site would experience scenarios like voltage sag, voltage swell, frequency deviations and unbalance which are common in the real world grid. When these systems are tested at laboratory, these scenarios do not exist and an almost stiff voltage source is what is usually seen. But, to qualify the grid-connected systems to operate at the site, it becomes essential to test them under the grid conditions mentioned earlier. The grid simulator is a hardware that can be programmed to generate some of the typical conditions experienced by the grid-connected systems at site. It is an inverter that is controlled to act like a voltage source in series with a grid impedance. The series grid impedance is emulated virtually within the inverter control rather than through physical components, thus avoiding the losses and the need for bulky reactive components. This paper describes the design of a grid simulator. Control implementation issues are highlighted in the experimental results.

Inductors are important energy storage elements that are used as filters in switching power converters. The operating efficiency of power inductors depend on the initial design choices and they remain as one of the most inefficient elements in a power converter. The focus of this paper is to explore the inductor design procedure from the point of efficiency and operating temperature. A modified form of the area product approach is used as starting point for the inductor design. The equations which estimate the power loss in core and copper winding are described. The surface temperature of the inductor is modelled using heat transfer equations for radiation and natural convection. All design assumptions are verified by actual experimental data and results show a good match with the analysis.

Problems like windup or rollover arise in a PI controller working under saturation. Hence anti-windup schemes are necessary to minimize performance degradation.Similar situation may occur in a Proportional Resonant(PR)controller in the presence of a sustained error input.Several methods can be employed based on existing knowledge on PI controller to counter this problem.In this paper few such schemes are proposed and implemented in FPGA and MATLAB and from the obtained results their possible use and limitations have been studied.

Design of higher order LCL filters that are used in grid-connected inverter applications involves multiple constraints. The filter requirements are driven by tight filtering tolerances of standards such as IEEE 519-1992 and IEEE P1547.2- 2003. Higher order LCL filters are essential to achieve these regulatory standard requirements at compact size and weight. This paper discusses the design procedure for these higher order LCL filters. The design procedure is analysed in per-unit basis so results can be generalized for different applications and power levels. This paper also gives guidelines for actual construction of the inductor based on a proposed fringing flux model. Experimental results of filtering characteristics show a good match with analysis in the frequency range of interconnected inverter applications.

Phase tracking system or phase locked loop (PLL) is an important part of the control unit of a grid connected power converter. Popular methods such as zero crossing detection (ZCD) and synchronous reference frame (SRF) PLL do not produce accurate phase information when grid is non-ideal. In this work a method to obtain accurate phase information when the grid voltages are unbalanced by adding a moving average filter to a SRF PLL has been proposed. The performances of the PLL have been experimentally verified for abnormal grid conditions such as unbalance, harmonics, voltage sag and swell, faults etc. Generally, during a fault phase voltages become unbalanced so this method can give better fault ride through capability to a power converter.

Distributed energy resources can provide power to local loads in the electric distribution system and benefits such as improved reliability. Microgrids are intentional islands formed at a facility or in an electrical distribution system that contains at least one distributed resource and associated loads. Microgrids that operate both electrical generation and loads in a coordinated manner can offer additional benefits to the customer and local utility. The loads and energy sources can be disconnected from and reconnected to the area or local utility with minimal disruption to the local loads, thereby improving reliability. This paper details the development and testing of a highspeed static switch for distributed energy and microgrid applications.

Grid integration of renewable energy based distributed energy resources (DERs) through pulse-width modulated (PWM) grid-tie inverters (GTI), is gaining importance owing to ever-increasing energy demand. Study of islanding behavior of such GTIs is critical for detecting island formation and for subsequently ceasing DER operation. The grid-interface structure of a GTI considered for islanding study typically consists of a parallel RLC network forming the load bank, along with grid and grid-impedance. Existing models for analysis of grid-interface are based on time-domain differential equations and are less insightful for analytical study of the ac phenomena occurring during and after island formation. In this paper, a dynamic-phasor based approach is investigated for modeling and analysis of grid-interface passive network system of a DER. A generic and simplified framework is proposed for developing polar coordinates based dynamic phasor models of passive networks, which are verified through simulation and experiments.