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Nowadays, single photon counting pixel hybrid detectors are becoming increasingly popular in high-energy physics, X-ray detectors for synchrotron applications, and medical imaging. Readout chips for these detectors usually have the area of a few square centimeters and are designed to be abutted on three sides. However, many applications require large-area detectors without dead areas. The through-silicon vias (TSVs) aim to minimize the dead area and in that way to enable development of four-side buttable large-area detectors. AGH, Krakow, and IZM, Berlin, have undertaken a common effort to apply TSV (via last) technology to the readout integrated circuit called UFXC32k containing a matrix of $128 \times 256$ pixels, with a pixel pitch of $75~\mu \text{m}$ and a total area of 2 cm2. The TSVs were applied to the 87 I/O pads located at the bottom of UFXC32k IC. A TSV diameter of $20~\mu \text{m}$ was chosen while the wafers were thinned to $100~\mu \text{m}$ . The redistribution layer and the array of pads for solder bumping were distributed at the bottom side of the chips. Two UFXC32k chips with TSVs were attached to a single, 320- $\mu \text{m}$ -thick silicon sensor and finally, the chip detector modules were attached to low-temperature co-fired ceramic boards. The $2 \times 2$ cm2 plug-in detector modules were successfully built and tested.

This paper presents a readout integrated circuit called UFXC32k, designed for hybrid pixel semiconductor detectors used in X-ray imaging applications. The UFXC32k integrated circuit, designed in a CMOS 130 nm process, contains about 50 million transistors in the area of $9.64\;\hbox{mm} \times 20.15\;\hbox{mm}$ . The core of the IC is a matrix of $128 \times 256$ square-shaped pixels of ${\hbox{75}}\;\mu\hbox{m}$ pitch. Each pixel contains a charge sensitive amplifier, a shaper, two discriminators, and two 14-bit ripple counters. The analog front-end electronics allow processing of sensor signals of both polarities (holes and electrons). The UFXC32k chip is bump-bonded to a pixel silicon sensor and is fully characterized using X-ray radiation. The measured equivalent noise charge for the standard settings is equal to $123\ {{\rm e}^ - }\;\hbox{rms}$ (for the peaking time of 40 ns) and each pixel dissipates $26\;\mu\hbox{W}$ . Thanks to the use of trim blocks working in each pixel independently, an effective offset spread calculated to the input is only $9\ {{\rm e}^ - }\;\hbox{rms}$ with a gain spread of 2%. The maximum count rate per pixel depends mainly on effective CSA feedback resistance. Dead time in the front end can be set as low as 85 ns. In the continuous readout mode, a user can select the number of bits read out from each pixel to optimize the UFXC32k frame rate, e.g., for a readout of 2 bits/pixel with 200 MHz clock, the frame rate is equal to 23 kHz.

In this paper, the design of 4 Gbps, 2.25 mW Scalable Low-Voltage Signaling (SLVS)-type transmitter is described. The analysis of circuit performance is concentrated on the minimization of common-mode voltage disturbances, while providing satisfactory eye diagram parameters and low power consumption. The edge aligner circuit utilization is proposed in order to minimize the time delay between the input positive and the input negative control voltage of the driver. Moreover, the effectiveness of two methods for driver output impedance correction is evaluated. Special emphasis is put on a reliable transmission path modeling, whose parameters influence an overall transmitter operation. The designed transmitter will be fabricated in 55 nm CMOS technology.

This paper presents design and measurement results of an integrated circuit dedicated to recording and detecting a wide range of biomedical signals. The chip is designed in 180 nm CMOS technology and occupies 1.5×1.5 mm 2 . It consists of 8 channels responsible for amplification, filtration and detection of biomedical signals. In order to satisfy the requirements of a wide range of neurobiological experiments, the main parameters of a single recording channel, such as voltage gain, frequency band, voltage offset and threshold detection, are controlled independently by on-chip digital registers. The recording part is divided into two separate channels, i.e. an Action Potential (AP) stage and a Local Field Potential (LFP) stage. The voltage gain of the AP and LFP stages can be switched between 55.7/50.3 dB and 50.3/45.1 dB respectively. Corner frequencies of a particular stage can be digitally controlled in a wide range, i.e. the upper cut-off frequency can be changed in the 20 Hz–2 kHz (LFP stage) while the lower cut-off frequency can be tuned at the 120 mHz–3 kHz (LFP and AP stage). The upper cut-off frequency of the AP stage is equal to 6.9 kHz. In addition, the area of the analog part of the recording channel is 0.04 mm 2 . A single recording channel is supplied from ±0.9 V and consumes about 4.8 µW of power while the Input Referred Noise is equal to 6.2 µV resulting in 4.92 of Noise Efficiency Factor (NEF).

The common mode rejection ratio (CMRR) strongly depends on matching and this effect is clearly visible in multichannel recording systems. Therefore, a method for improving the CMRR in multichannel recording integrated circuits (ICs) dedicated to biomedical experiments is reported. The method is based on balancing the amplifier's inputs using leakage currents. The proposed technique was verified in the 64 channel IC processed in CMOS 180 nm. The measurement results show that with use of the proposed balancing technique the CMRR is increased by more than 30 dB. Additionally, in comparison to conventional CMRR measurement methods, the proposed solution is attractive in three ways: its on-chip implementation simplicity, fast operation, and it is especially suitable for modern nanometre processes.

This paper presents a low noise low power neural recording amplifier that occupies a very small silicon area and is suitable to integrate with multielectrode arrays in cortical implants. We analyze main problems in neural recording systems processed in modern submicron technologies, i.e., leakage currents, ability to obtain very large and precisely controlled MOS based resistances and spread of the main system parameters from channel to channel. We also introduce methods allowing to mitigate them. Finally, we present methods allowing to calculate optimal channel dimensions of the recording channel's input transistors in order to obtain the lowest Input Referred Noise (IRN) for given power and area requirements. The proposed methodology has been applied in the 8-channel integrated recording ASIC dedicated to the broad range of neurobiology experiments. Each of the recording channels is equipped with the control register that enables to set main channel parameters independently. Thanks to this functionality, the user is capable of setting lower cut-off frequency within the range of 300 mHz-900 Hz. The upper cut-off frequency can be switched either to 30 Hz-290 Hz or 9 kHz, while the voltage gain can be set either to 260 V/V or 1000 V/V. A single recording channel is supplied with 1.8 V and consumes only 11 μW of power, while its input referred noise is equal to 4.4 μV resulting in NEF equal to 4.1.

The article reports on the measurement results of a 64 channel integrated circuit dedicated to neurobiological experiments and processed in the CMOS 180nm technology. It also provides an analysis of its parameters spread from channel to channel, its origin and a proposition of a circuit that allows for a precise bandwidth correction in the wide tuning range. The presented work is focused on improving the uniformity of the lower corner frequency of a recording channel with the respect to low power consumption and low area occupation of the calibration blocks what may be especially attractive in the circuits where area occupation and power consumption are a prime of concerns.

A 64-channel ASIC (SXDR64) aimed to work with both AC and DC coupled detectors (Si, CdTe, GaAs), in a single photon counting mode with an energy window has been developed. Every channel of the ASIC consists of a charge sensitive amplifier, a pole-zero cancellation circuit, a 4th order shaper with programmable gain from 14 μV/e- to 50 μV/e- and peaking time from 115 ns to 380 ns, a base-line restorer, two independent discriminators, and two 20-bit counters. Control and readout of the chip are done using on-chip LVDS drivers/receivers. The ASIC can work with input leakage currents in the range from -10 nA up to 7 nA. The ENC obtained with an AC-coupled Si detector is 120 e- for a peaking time Tp=115 ns and Cdet=1.2 pF. With a DC-coupled CdTe detector, the ENC is 210 e- rms for a peaking time Tp=380 ns and Cdet=2 pF and the leakage current Idleak=0.15 nA. The implemented trim DACs at the discriminator inputs allows to minimize the effective threshold spread to 8 e- rms (at one sigma level). The ASIC is designed in a CMOS 0.35 μm technology and its total area is 4800×5000 μm2.

64 Channel ASIC for Neurobiology ExperimentsThis paper presents the design and measurements of 64 channel Application Specific Integrated Circuits (ASIC) for recording signals in neurobiology experiments. The ASIC is designed in 180 nm technology and operates with ± 0.9 V supply voltage. Single readout channel is built of AC coupling circuit at the input and two amplifier stages. In order to reduce the number of output lines, the 64 analogue signals from readout channels are multiplexed to a single output by an analogue multiplexer. The gain of the single channel can be set either to 350 V/V or 700 V/V. The low and the high cut-off frequencies can be tuned in 9 ÷ 90 Hz and in the 1.6 ÷ 24 kHz range respectively. The input referred noise is 7 μV rms in the bandwidth 90 Hz - 1.6 kHz and 9 μV rms in the bandwidth 9 Hz - 24 kHz. The single channel consumes 200 μW of power and this together with other parameters make the chip suitable for recording neurobiology signals.

The paper presents a readout integrated circuit called UFXC32k designed for hybrid pixel semiconductor detectors used in X-ray imaging applications. The UFXC32k integrated circuit designed in CMOS 130 nm process, contains about 50 million transistors in the area of 9.64 mm × 20.15 mm. The core of the IC is the matrix of 128 × 256 square shaped pixels of 75 μm pitch. Each pixel contains a charge sensitive amplifier, a shaper, a discriminator, correction circuits and two 14-bit counters. The data is read out via 8 Low Voltage Differential Signaling (LVDS) outputs. The UFXC32k chip is bump-bonded to a pixel silicon sensor and fully characterized in X-ray radiation. The measured equivalent noise charge is equal to 123 e− rms (for the peaking time of 40 ns) and each pixel dissipates 26 μW. Thanks to the use of multilevel offset correction, an effective offset spread calculated to the input is only 9 e− rms with the gain spread of 2 %.

The article describes a System on Chip (SoC) for multi-channel wireless recording of nerve tissue electrical activity. Specificity of neural signals, the method of registration by using microelectrode arrays and requirements for the SoC are presented. Eventually, individual elements of the system such as conditioning module, analogue multiplexer, A/D converter, radio transmitter and system controller are discussed.

This paper presents the design and simulation results of a reconfigurable stimulator dedicated to multichannel neurobiology experiments. The proposed circuit employs a bipolar current stimulation and is based on only one operational amplifier that is dynamically switched among anodic and cathodic phases. The both multibiasing and current reusing techniques are used to save power consumption and area occupation of the stimulator. Additionally, the special attention was paid to increase the voltage compliance of the circuit what resulted in 91% of the voltage supply voltage compliance while keeping high output impedance in tens of mega-ohm range. The main current stimulator parameters, i.e. the current polarity and its value, duration and frequency of the current pulses, are controlled digitally. Each of the three current ranges, i.e. 2 μA, 10 μA, 200 μA, are controlled with 5-bit resolution. To keep the current pulses uniformity from channel to channel at a high level the MOS body biasing is used. The current stimulator is supplied from 3.3 V and is designed in CMOS 180 nm.

This paper presents the design and simulation results of the ultrafast LVDS I/O interface designed in 40 nm CMOS process. The LVDS transmitters and receivers were designed to support a data transfer of a multichannel Integrated Circuit dedicated for readout of hybrid pixel semiconductor detectors used for X-ray imaging applications. The transmitter is based on the current switching bridge architecture while the receiver is built of the inverting comparator with hysteresis. The LVDS I/O interface is supplied from 2.5 V and 0.9 V supply voltage. The transmitter and receiver occupy respectively 0.1 mm 2 and 0.009 mm 2 of chip area. The static/dynamic power consumption of the transmitter and receiver are respectively equal to 17.9/26.4 mW and 7.1/12.1 mW.

We present a prototype chip built in a 40 nm CMOS process for readout of a pixel detector. The prototype chip has a matrix of 18×24 pixels with a pixel pitch of 100 µm. It can operate in both: the single photon counting (SPC) mode and the C8P1 mode. In the SPC mode using the high gain setting the measured ENC is 84 e− rms (for the peaking time of 48 ns), the gain is 79.7 µV/e−, while the effective offset spread is 24 e− rms. In the C8P1 mode, the chip reconstructs full charge deposited in the detector, despite the charge sharing, and it points to a pixel with the largest charge deposition. The chip architecture and preliminary measurements are reported.

Hybrid pixel detectors working in a single photon counting mode are very attractive solutions for material science and medical X-ray imaging applications. Readout electronics of these detectors has to match the geometry of pixel detectors with an area of readout channel of 100 μm × 100 μm (or even less) and very small power consumption (a few tens of μW). New solutions of readout ASICs are going into directions of better spatial resolutions, higher data throughput and more advanced functionality. We report on the design and measurement results of two pixel prototype ASICs in nanometer technology and 3D technology which offer fast signal processing, low noise performance and advanced functionality per single readout pixel cell.

A 64-channel Neuro-Stimulation-Recording chip named NRS64 for neural activity measurements has been designed and tested. The NRS64 occupies 5×5 mm2 of silicon area and consumes only 25 µW/channel. A low cut-off frequency can be tuned in the 60 mHz – 100 Hz range while a high cut-off frequency can be set to 4.7 kHz or 12 kHz. A voltage gain can be set to 139 V/V or 1100 V/V. A measured input referenced noise is 3.7 µV rms in 100 Hz – 12 kHz band and 7.6 µV rms in 3 Hz – 12 kHz band. A digital correction is used in each channel to tune the low cut-off frequency and offset voltage. Each channel is equipped additionally with a stimulation circuit with an artifact cancellation circuit. The stimulation circuit can be set with 8-bit resolution in six different ranges from 500 nA – 512 µA range.

We report on the analysis, simulations and measurements of both noise and high-count rate performance of a single photon counting integrated circuit called UFXC32k designed for hybrid pixel detectors for various applications in X-ray imaging. The dimensions of the UFCX32k designed in CMOS 130 nm technology are 9.63 mm × 20.15 mm. The integrated circuit core is a matrix of 128 × 256 squared readout pixels with a pitch of 75 μm. Each readout pixel contains a charge sensitive amplifier (CSA), a shaper, two discriminators and two 14-bit ripple counters. The UFXC32k was bump-bonded to a silicon pixel detector with the thickness of 320 μm and characterized with the X-ray radiation source. The CSA feedback based on the Krummenacher circuit determines both the count rate performance and the noise of the readout front-end electronics. For the default setting of the CSA feedback, the measured front-end electronics dead time is 232 ns (paralyzable model) and the equivalent noise charge (ENC) is equal to 123 el. rms. For the high count rate setting of the CSA feedback, the dead time is only 101 ns and the ENC is equal to 163 el. rms.

This paper presents a design and measurements of multichannel integrated circuits dedicated to recording of neurobiological signals. 64 recording channels have been implemented in a single chip using a commercially available CMOS 180 nm process. A single recording amplifier consumes only 25 µW from 1.8 V supply and occupies 0.13 mm2 of the silicon area. Its main parameters such as the low/high cut off frequencies and the voltage gain are controlled thanks to the on-chip register. User is able to change the low cut off frequency in the 60 mHz – 100 Hz range in each channel independently while the high cut off frequency and the voltage gain can be set to 4.7 kHz / 12 kHz and 139 V/V / 1100 V/V respectively. The input referred noise depends on the bandwidth of the recording channel and is equal to 3.7 µV (100 Hz – 12 kHz) or to 7.6 µV (3 Hz – 12 kHz). This paper deals with problems that are present in a multichannel integrated recording electronics for neurobiology experiments such as: ability to record input signals in the frequency range below a single Hz, and the spread of the cut off frequencies from channel to channel in such systems. Up to our knowledge the solution presented in this paper is the first one reporting the multichannel IC that is able both to record extremely low frequency signals in each channel with a small spread of this parameter from channel to channel.

We present the design and measurements of a novel 64 channel ASIC dedicated for recording and stimulation of neural network activity. Chip is designed in submicron CMOS 180nm technology, occupies 5×5 mm2 of silicon area, and consumes only 25 μW/channel. The low cut-off frequency can be tuned in the range 60 mHz-100 Hz while the mean high cut-off frequency is 4.7 kHz or 12 kHz. The recording channel voltage gain may be also changed. Mean measurement values show it may be either 139 V/V or 1100 V/V. The measured input referenced noise is 3.7 μV rms in band 100 Hz-12 kHz and 7.6 μV rms in band 3 Hz-12 kHz. For the input signals amplitude 1.5 mV, the THD is 1%. In order to satisfy requirements concerning spread of the main parameters of the multichannel system, each channel is equipped with the two corrections DAC's. These allow to obtain voltage gain equal to 139 V/V with the standard deviation std = 0.67 V/V, and low cut-off frequency equal to 60 mHz with the std = 30 mHz only. Each channel is equipped additionally with a stimulation circuits allowing to generate stimulation pulses in the 125 nA-512 μA current range with 8-bit resolution. All ASIC configurations are set thanks to on-chip digital register controlled by the on-chip LVDS receivers.

We present two different approaches to the multichannel recording ASICs dedicated for neurobiology experiments. The ASICs are processed in 180nm CMOS technology and occupy the same silicon area of 5×2.3 mm2. Presented integrated circuits include 64 recording channels and have a possibility to tune their low and high cut-off frequencies. Each recording channel consumes about 200 μW of power and is characterized by the input referred noise as low as 6 μV rms. Both presented ASICs have good uniformity concerning the spread of their electrical parameters (like gain, corner frequencies, offsets, noise) from channel to channel. In order to decrease the number of output wires the 64:1 analog multiplexer is used in both cases. This paper presents the architecture, the layout, and the measurement results of the ASICs. Additionally it reports about the system we have built for neurobiology experiments that comprises of presented ASICs and micromachined recording electrodes. We show the preliminary measurements of action potentials from the thalamus of the rat under urethane anesthesia.

This paper presents the design and measurements of a low noise multi-channel front-end electronics for recording extra-cellular neuronal signals using microelectrode arrays. The integrated circuit contains 64 readout channels and was fabricated in CMOS 0.18 microm technology. A single readout channel is built of an AC coupling circuit at the input, a low noise preamplifier, a band-pass filter and a second amplifier. In order to reduce the number of output lines, the 64 analog signals from readout channels are multiplexed to a single output by an analog multiplexer. The chip is optimized for low noise and matching performance with the possibility of cut-off frequencies tuning. The low cut-off frequency can be tuned in the 1 Hz-60 Hz range and the high cut-off frequency can be tuned in the 3.5 kHz-15 kHz range. For the nominal gain setting at 44 dB and power dissipation per single channel of 220 microW the equivalent input noise is in the range from 6 microV-11 microV rms depending on the band-pass filter settings. The chip has good uniformity concerning the spread of its electrical parameters from channel to channel. The spread of gain calculated as standard deviation to mean value is about 4.4% and the spread of the low cut-off frequency is on the same level. The chip occupies 5x2.3 mm(2) of silicon area.

This paper presents the design and simulation of the 64 channel analogue multiplexer for neural signal recording system designed in CMOS 180 nm technology. Single channel sampling rate is 100 kHz and linear range of the input signal is +/-400 mV. For noise cancellation caused by digital part of the differential architecture with dummy channel has been used.

We present the design and simulation of the neural recording amplifier in the CMOS 180 nm technology. Amplifier is capable of recording signals from mHz range up to kHz range while rejecting large DC offset generated on the electrode-electrolyte interface. Its band may be control to span over all interesting biopotential signals (low cutoff frequency from 73 mHz to 125 Hz while the upper cutoff frequency from 1.85 kHz to 16.5 kHz). Due to its low input referred noise 4.5 muV (integrated from 1 mHz to 100 kHz), low power consumption 28 muW per one channel, small occupied area 0.094 mm2 and small spreads of its main parameters designed amplifier is a good candidate for multichannel neural recording system.

This paper presents a design of a circuit for Common Mode Rejection Ratio (CMRR) correction in Integrated Circuits (IC) dedicated to neurobiology experiments. The design is realized in CMOS 180nm process and will be adopted in a multichannel IC. Description of the design is preceded by CMRR measurement results of a former prototype IC where a novel CMRR correction method was adopted. A main requirement of the presented design was its ultra low power consumption, small area occupation and improved correction precision comparing to our former work. The paper also provides a review of solutions that aim at on-chip implementation of correction circuits used for channel-to-channel spread minimization of main IC's parameters.

This paper presents an approach for main parameters uniformity improvement from channel to channel in integrated circuit dedicated to multi-point neurobiological recordings. We show that if the conditioning channel size and power consumption are very limited, additional correction circuits are necessary to key parameters spread lowering. The method has been implemented in a 64-channel circuit fabricated in 180 nm CMOS technology and resulted in tenfold reduction of corner frequency spread (from 59% down to 4%) and fourfold reduction of DC offset (from 31.6% down to 7.5%). The correction circuit has also been used in a novel optimization method which allows for more than 30 dB Common Mode Rejection Ratio increase. It is also worth mentioning that the proposed methodology is very efficient and has minor impact on the overall channel size and power consumption A single recording channel consumes 8.5 μW of power and occupies 0.065 mm2 of silicon area while its Input Referred Noise is equal to 5μV RMS .