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Temperature dependence of propagation delay time and power-delay product in Si MOSFETs (fabricated using 1 μm X-ray lithography) has been measured using 19-stage ring oscillators. The delay time was found to decrease with lowering temperature. As a numerical example we found that a delay time of 30 ps at room temperature decreased to 22 and 18 ps at 77 and 4.2 K respectively, and increased to 38 at 400 K. The power showed a slight increase with decreasing temperature, while the power-delay product decreased. The decrease in the delay time has been explained in terms of increase in the electron drift velocity with decreasing temperature, as well as decrease in one component of the capacitive load, namely the source-drain junction capacitance, due to carrier freeze-out.

We present results on very high-speed low-power devices and circuits fabricated using a NMOS technology scaled to submicron dimensions. These results illustrate the electrical behavior of single minimum-size devices, and present the performance of several submicron circuits, such as ring oscillators, a 3-GHz divide-by-two counter and a 90- MHz 16 × 16 multiplier.

We present new experimental results on optimally scaled MOSFETs with channel lengths below 0.25 µm. These devices have been fabricated using a modified NMOS process. All patterns have been defined by direct-beam writing using both positive and negative electron resists. The gate oxide thickness of 80A together with properly adjusted ion implantation steps yields device thresholds of 0.5 V. All heat treatments have been kept as short as possible to ensure very shallow source-drain junctions. All contact structures are scaled to 1 × 1 µm window features. Finished devices show excellent performance. Long-channel-like behavior is preserved for supply voltages below 2.5 V. The subthreshold slope is 88 mV/decade. Current drive capabilities are the highest ever reported for silicon MOSFETs. The devices exhibit outstanding transconductance values between 270 and 300 mS/mm.

A CMOS process is described that is designed to optimize the transistor characteristics of the n-channel and p-channel devices simultaneously. This is achieved by making the n- and p-channel devices symmetric in channel doping, junction depths, sheet resistivities and threshold voltages. The resulting devices have CoSi 2 source/drains with sheet resistivities of 1.5-2 Ω/square, n+ and p+ polysilicon/TaSi 2 gate structures, Threshold voltages of 0.4 V and 1.5 µm separation between active to tub-edge regions. Diode characteristics of the CoSi 2 /n+ and CoSi 2 /P+ are determined to be as good as non-silicided silicon junctions. Maintaining the proper doping for the connected n+ and p+ polysilicon/silicide gates is demonstrated. Ring oscillator delays of 110 ps at 3.5 V are observed for devices with 0.5 µm channel lengths. The ring oscillator circuits are still operational at power supply voltages of 1.0 V due to the low threshold voltage of the transistors.

We have fabricated very high speed, low power devices and circuits using a submicron NMOS technology. Our results illustrate the electrical behavior of single minimum size devices, and present the performance of several submicron circuits, such as ring oscillators, a 3 GHz divide-by-two counter and a 90 MHz 16 × 16 multiplier.

The theory for bipolar transistors operated at high collector currents is weak. Controversy exists as to when (or if) lateral current spreading dominates over the Kirk effect. This paper attempts to answer this question. The output characteristics of silicon bipolar transistors in the common emitter configuration are analyzed in detail. The analysis proceeds by extracting the values of transistor generation current (due to small amounts of collector multiplication) from experiment, fitting these values to a model which accounts for the modulation of the collector depletion layer by mobile space charge and the lateral spreading of collector current. It is found that a continuous and gradual increase in collector effective area occurs as the collector current increases. In this manner the deleterious effects of high current density are moderated. By accounting for this effect, cut-off frequency calculations are brought into good agreement with experiment. As an independent check on the validity of the analysis, electron ionization rates are obtained, which are in good agreement with values in the literature. Effects associated with emitter crowding are also shown to be unimportant in the structures investigated.

The MOSFET with doubly diffused drain has been proposed as a solution to the problem of degradation in small MOSFETs. We find good agreement between measured gate current and values calculated assuming that the gate current is due to hot channel electrons thermionically emitted into the gate oxide.

Silicon diode microwave oscillators and amplifiers employing two different diode structures are reported. These diodes employ the avalanche transit-time properties originally discussed by Read. A simple p-n junction has produced 13 mW of CW power at 10.5 Gc/s with 0.5 percent efficiency as an oscillator. A similar diode, when incorporated into a circulator coupled amplifier circuit, produced 30 Mc/s bandwidth with 20 dB of gain. Noise figures in the 50 to 60 dB range were obtained in preliminary measurements. Experimental results with these diodes are shown to be in qualitative agreement with the small-signal theory of Misawa. A double diffused "hyperabrupt" diode has also been fabricated as prescribed by Read. These diodes have produced 19 mW of CW power at 5 Gc/s with 1.4 percent efficiency and 13 mW with 1.5 percent efficiency.