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In this paper, a peak efficiency tracking technique to improve the efficiency of switched capacitor (SC) DC–DC converters as the load varies is presented. A peak efficiency tracking circuit based on feedback control over the switching frequency is implemented for this scope. The basic idea of the proposed technique is to adjust the switching frequency according to the load. The technique is successfully implemented in a SC DC–DC converter to be embedded in detector pixels for the Large Hadron Collider (LHC) experiment at the Conseil Européen pour la Recherche Nucléaire (CERN) of Geneve. It is realized in 65 nm bulk CMOS technology with an occupied area of 1.31 mm2. This converter provides an 800 mV output voltage from a 1.2 V supply. The load of the DC–DC converters is modeled as a resistor, RLOAD, that has 4 Ω nominal value but it can range from 2.67 up to 10 Ω. At 10 Ω RLOAD, a 6% efficiency improvement is reached with respect to the typical approach consisting in keeping constant the switching frequency at the optimum value for RLOAD nominal value.

The reduction of the nominal supply voltage of CMOS technologies with scaling comes with the decrease of the maximum tolerable voltage of the devices. This poses challenges in implementing circuit blocks that are compliant with standardized communication protocols or deal with off-chip signals in voltage domains larger than the nominal supply (e.g., 1.8 V, 3.3 V, 5 V). Design techniques such as cascoding, voltage shifting and adaptive biasing are effective at removing the need for customized voltage resistant input/output (I/O) devices since they prevent intolerable voltage drops. However, at the input of multiple-channel blocks, the design of switches of multiplexers results critical as the input and the output nodes can assume values beyond the signal range, causing harmful biasing configurations. This paper presents the architecture of a switch for input channel multiplexers able to handle signals up to twice the nominal supply voltage of the employed devices. Its effectiveness has been proved by implementing a 1.6V switch with the core MOS transistors of the 28nm CMOS technology with 0.96V nominal supply voltage. The comparison with a benchmark switch based on 1.8V I/O devices showed that both a larger area (slightly more than twice) and static current consumption ( $40\mu \text{A}$ ) are required.

An energy-efficient, wide dynamic-range (DR) CMOS analog front-end (AFE) for chemiresistive sensors is presented. The circuit is specifically designed for the Metal Oxide (MOX) gas sensors, a special technology of chemiresistive sensors, broadly diffused in modern portable devices due to their low-cost and simplicity of use. Energy efficiency is mandatory for the AFE in order to prolong the battery life that supply these devices. The proposed circuit implements the resistance-to-time (R-to-T) conversion of the sensor’s resistance by adopting a relaxation oscillator-based architecture. A limiting resistor in series with the sensor is introduced for reducing the circuit’s energy-per-measurement (EpM), while mitigating the error due to the sensor’s parasitic capacitance. The analysis of the circuit is presented with emphasis on the design trade-off between error due to the sensor’s parasitic capacitance and power consumption on one side and read-out sensitivity on the other. The chip prototype is realized in AMS $0.35 ~\mu m$ process and has been tested in the DR between $100\Omega $ and $4.7M\Omega $ with an accuracy less than 0.1% and a precision less than 0.029%. The efficacy of the presented AFE is proved by adopting the circuit in a real chemical environment with a commercial sensor. The proposed AFE shows a maximum EpM of $296nJ$ which is three times better than the state of the art.

This paper presents a fully electrical dc–dc converter designed for thermoelectric generator (TEG) for energy harvesting applications. The proposed flexible TEG has been achieved by a screen printing technology on a 80 $\mu \text{m}$ thick common paper and thin Kapton foil and integrates 280 thermocouples for an output voltage of about 75 mV with 5 K of thermal gradient. In order to step up the voltage at the output of the thin-film flexible TEG, a dc–dc converter has been designed. This latter operates with an input voltage ranging from 80 up to 370 mV. The proposed dc–dc converter achieves an automatic control based on pulsewidth modulation, ensuring 1 V output voltage. The control circuit includes two sections. The first one provides a forward control operating in the 80–150 mV input voltage range. The second one operates a feedback control, as the output voltage of TEG is higher than 150 mV. The dc–dc converter is implemented in a 65 nm CMOS technology, achieving a 73% peak efficiency.

An architecture of a switched-capacitor integrator that includes a charge buffer operating in an open-loop is hereby proposed. As for the switched-capacitor filters, the gain of the proposed integrator, which is given by the input/output capacitor ratio, ensures desensitization to process, voltage, and temperature variations. The proposed circuit is suitable for low voltage supplies. It enables a significant power saving compared to a traditional switched-capacitor integrator. This was demonstrated through an analytical comparison between the proposed integrator and a traditional switched-capacitor integrator. The mathematical results were supported and verified by simulations performed on a circuit prototype designed in 16 nm finFET technology with 0.95 V supply. The proposed switched-capacitor integrator consumes 76 &micro, W, resulting in more than twice the efficiency for the traditional closed-loop switched-capacitor filter as an input voltage equal to 31.25 mV at 7 ns clock period is considered. The comparison of architectures was led among the proposed integrator and the state-of-the-art technology in terms of the figure of merit.

This paper analyzes the performance of amplification stages when they are used to buffer reference voltages. This topic is particularly interesting for Successive Approximation Register Analog to Digital Converters (SAR-ADCs) whose efficiency was tremendously pushed down during last years. A conventional solution for a reference buffer including a closed loop single stage opamp is firstly presented in order to individuate its limits. The conventional solution is used as benchmark for the proposed buffer circuit solution. It includes a reconfigurable circuit made by a charge pump, which enables a rapid charge of the output capacitive load. After the charging phase, the circuit is commutated into a closed loop opamp to let the feedback take the control of the output voltage. Both circuits were designed in CMOS 28nm technology with 1V supply. The proposed circuit has about half of the power consumption of the conventional one, 398μW and 774μW respectively, considering the same settling error.

This paper presents an ultra-low power DC–DC converter to be embedded into body sensor nodes. The proposed DC–DC converter is used to step-up the voltage at the output of a micro-thermoelectric generator up to a usable supply voltage between 0.42 and 1.05 V. Measurements have been conducted on ten available samples. The resulting mean value of the minimum input voltage is 96 mV. At the minimum input voltage, the power consumption is only 0.23 $\mu \text{W}$ . The operating temperature ranges from −40 °C to 100 °C.

In this letter, a fully-integrated RF-DC converter operating at the HF RFID working frequency (13.56 MHz) and realized in 350 nm CMOS technology is presented. It is based on a Dickson's rectifier, a Pelliconi's charge pump driven by a 50 kHz ring oscillator, and a voltage monitor. Mathematical model is developed and verified through simulations and measurements. Results show a sensitivity of −19 dBm with related output voltage of 0.5 V. Moreover, taking advantage from the internal voltage monitor, the suitability of the proposed architecture to pilot RFID-based sensor boards has been proved.

Thermoelectric energy harvesting represents a promising approach to partially or totally supply ultra-low power wearable devices, by using the human body heat as energy source. Few works were published on wearable and truly ready-to-use TEGs. The work presented in this contribute proposes development and assessment of operational properties of a system composed by a flexible heat sink free thermoelectric generator (TEG) and a DC–DC ASIC converter with 80 mV start-up input voltage. For a first functional investigation, a prototype of 45 thermocouples into a footprint area of about 2.2 × 10−3 m2 was fabricated and tested to evaluate its thermoelectric performance stand-alone and coupled with the DC–DC converter. A mean Seebeck coefficient of about 60 µV/K for pn couple was calculated from experimental data, and a power of about 27 nW was measured at 10 K on matched load of about 6.8 kΩ. A temperature difference of about 1.8 ℃ was achieved between the junctions in working conditions next to those typical of human body wearing in indoors.

A 3rd-order 132MHz cut-off frequency low-pass filter in 28nm CMOS-bulk technology is presented. Challenges related to the design of analog circuits in 28nm CMOS-bulk process node have been faced and mitigated operating at both architecture and circuit design level. The filter is based on an improved Active-gm-RC structure, where both poles of a Miller-compensated Opamp have been used for synthesizing the 3rd order filter transfer function. The proposed circuit solution enables high linearity (IIP3=11.5dBm at 21&22MHz input tones) even if the supply voltage is limited to 0.9V. Moreover, the power consumption is kept as low as 340μν without that the Signal-To-Noise ratio (60dB) is penalized. The achieved Figure-of-Merit is 164dB resulting the highest with respect to the state-of-The-Art.

A single-branch third-order low-pass filter with an ultracompact die size and extensive bandwidth (BW)-power scalability is described. It unifies a source follower , a stackable floating active inductor, and a feedforward capacitor to constitute a transistorized- LC-ladder topology with a stable pole-zero transfer function over a wide range of tunable BW. Differentially, only eight transistors and five untuned capacitors are required. Fabricated in 0.18- μm CMOS, the prototype occupies 0.014- mm2 die size. By scaling the bias current (and, hence, the power), the flexible BW measures 0.8 kHz at 1.25 nW and 0.94 GHz at 3.99 mW.

In this paper, a fourth-order continuous-time follow-the-leader-feedback (FLFB) low-pass (LP) filter is presented. The outstanding FLFB noise behavior is exploited to minimize power consumption. This is achieved by means of customized implementation solutions based on combination of Active- RC /Active- $g_{m}$ - RC cells. The 0.18- $\mu \text{m}$ CMOS prototype performs 22.5-MHz −3 dB LP frequency response. Large linearity and dynamic range were achieved resulting in 21.5-dBm in-band (iB) IIP3 and 87- $\mu \text{V}_{\mathrm {RMS}}$ input referred iB integrated noise. The SNR for a −40 dB HD3 is 63 dB. The overall power consumption is 12.6 mW (i.e., 7 mA from a 1.8-V supply). The efficiency of the proposed technique is demonstrated by the achieved figure-of-merit (150.8 dB $\cdot ~\text{J}^{-1})$ , which favourably compares to the state-of-the-art active- RC analog filters.

A 28 nm CMOS-bulk lowpass analogue filter architecture is hereby proposed. The filter is based on an improved Active-Gm -RC structure, where both poles of a Miller-compensated operational amplifier (OPAMP) have been used for synthesising a third-order filter. Several well-known issues related to the 28 nm process node have been hereby mitigated by proper circuit/design techniques, enabling large signal-to-noise ratio (SNR) and 13.5 dBm IIP3. The proposed circuital solution performs 59 dB-SNR at 340 µW power consumption from a single 0.9 V supply-voltage. This allows one of the higher figure-of-merit (156 dB) in sub-1 V analogue filters state of the art.

In this paper, a UHF-RFID power management circuit is presented. It is able to power body sensor networks nodes, starting from -25dBm UHF-RFID input signal power. It is based on an initial Dickson's RF-DC rectifier circuit, followed by an ultra-low-voltage integrated boost converter, realized in 180nm CMOS technology, that is used to further step-up of the rectified DC-voltage and to guarantee the RF-to-load isolation. Measurements demonstrate the ability of the power management circuit to provide 400mV output voltage when a -25dBm continuous wave at 866.5MHz (European UHF RFID frequency) is applied at the input. © 2015 IEEE.

A low power 7.5---10.6 GHz frequency synthesizer for impulse radio ultra-wide band (IR-UWB) is designed and fabricated in 65 nm CMOS technology. The synthesizer is based on an integer-N type-II 4th-order PLL architecture. A 7-bit voltage-controlled oscillator with 31 % tuning range and a set of high-speed dividers are used to synthesize all the carriers defined by the IEEE standard 802.15.4a. The frequency dividers are based on true single phase clock logic resulting in compact implementation and low power consumption. The 0.33 mm2 fully integrated synthesizer consumes 5.13 mA from a 1.2 V supply. With a 3-dB closed-loop bandwidth of 100 kHz, the settling time is 15 µs. It features

A 4th-order single-loop follow-the-leader-feedback (FLFB) low-pass continuous-time filter in CMOS 0.18 μm is hereby presented. The outstanding FLFB noise behaviour is exploited to allocate the power consumption to linearity performance. The low-pass filter prototype features 22.5 MHz-3 dB frequency, 21.5 dBm-IIP3 and 76 μVRMS input referred in-band integrated noise. The overall power consumption is 7 mA from a 1.8 V supply voltage. The signal-to-noise ratio for a -40 dB-total harmonic distortion is 69 dB.

An improved Active-Gm-RC filter architecture is proposed in this paper. With respect to the biquad Active-Gm-RC cell, this architecture exploits the second pole of the Opamp to increase the filter order up to 3, while maintaining single Opamp topology. This reduces the required power per pole. A prototype of the low-pass filter has been designed in 28nm CMOS technology. The filter power consumption is 340μW with a 0.9V voltage supply, cut-off frequency is 150MHz achieving a Figure-of-Merit of 165dB.

In this paper, a RF-DC voltage multiplier operating at 13.56MHz (in the European HF RFID standard band) with -19dBm sensitivity is presented. It is made by a Dickson's RF-DC rectifier and an additional Pelliconi's charge pump driven by a fully integrated 50kHz ring oscillator. Mathematical model is developed and verified through measurements. Silicon prototypes have been realized in 350nm CMOS technology. Measurements show an output voltage ranging from 0.5V up to 3.11V. © 2015 IEEE.

The growing demand of wearable and low cost sensor devices, pushed the development of key enabling technologies able to transfer the well know materials on cheap substrates, keeping the capabilities of developed systems to integrate energy harvesting, sensing and communication functions. A flexible thermoelectric generator (TEG) with a fully electrical, low startup voltage and high efficiency DC-DC converter is presented in this paper. The proposed generator has been produced by screen printing technology on 80 microns thick common paper and thin Kapton foil and integrates about 280 thermocouples, for an output voltage of about 75 mV with 5 K of thermal gradient, useful for wearable-oriented applications. To increase the voltage provided by TEG, a DC-DC converter is designed. It operates with an input voltage (V in ) range from 40mV up to 400mV. By means the pulse width modulation (PWM), the DC-DC converter achieves an automatic control, ensuring an 1V output voltage. It is composed of two control section: the feedforward control circuit operates with an input voltage ranging from 40mV up to 150mV. As the output voltage of TEG is higher than 150mV, the feedback control circuit starts to operate, achieving an automatic control of the output voltage of the boost converter. The DC-DC converter is implemented in 65nm CMOS technology and its peak efficiency is 85%.

In this paper a highly-linear software defined radio front-end (LNA and Mixer) for wireless sensor networks in the 5.8-to-13 GHz frequency range is presented. It is suitable to IEEE 802.15.4a and IEEE 802.15.4a and upcoming different standards. The RF front-end features a very high robustness to out-of-band interference (OBI) thanks to mixer-based RF blocker filtering. This allows to remove any dedicated filtering at the antenna reducing costs. The low noise amplifier exploits a common-gate (CG) stage in parallel to a common-source (CS) performing the single-ended to differential-ended conversion avoiding off-chip balun stage. The analog front-end provides 21.6–25.6 dB conversion gain, 2.16–4 dB noise figure and 2.6–5.1 dBm in-band IIP3 over 5.8 GHz to 13 GHz. It tolerates −5 dBm blockers at 100 MHz offset for input-referred 1-dB desensitization. This work has been designed in 65nm CMOS technology, 1.2V supply and 9 mA current consumption.

In this paper, a "composite" source-follower is presented. Using a positive-feedback, the structure synthesizes complex poles with a single branch. This allows to realize a single-branch biquadratic cell. Moreover, due to the intrinsic feedback present in any source-follower, the proposed cell performs larger linearity for smaller Vov(= VGS -V TH). This is the opposite of other active filters and allows saving the power otherwise used to increase linearity. A fourth-order prototype satisfy typical WLAN 802.11.a/b/g baseband filter specifications has been realized in a 0.18 μm CMOS at 1.8-V supply. It achieves a 17.5-dBm IIP3 and a -40 dB HD3 for a 600-mVpp_diff input signal amplitude. A 24-μVrms noise gives a DR = 79 dB, with 2.25-mA current consumption. © 2006 IEEE.

In this paper, an energy harvesting system composed by a flexible thermoelectric generator (TEG) with a DC — DC converter is shown. The proposed generator has been produced by screen printing technology on 80μm thick common paper and thin Kapton foil and integrates about 280 thermocouples, for an output voltage of about 75mV with 5K of the thermal gradient, useful for wearable — oriented applications. To increase the voltage provided by TEG, a DC — DC converter is implemented in 65nm CMOS technology. It operates for an input voltage (Vjn) range from 80mV to 370mV. This converter achieves an automatic control based on pulse width modulation (PWM), that ensure 1V output voltage (VOUT), for the various input voltages. The peak efficiency is 73% at 370mV of input voltage.

Wireless technology has been developing fast for years and it is spreading to new areas of everyday life. One of the newest areas is healthcare and welfare sector where it can be a significant way to save costs and improve existing procedures. The coming years are going to be challenging as the population, in the developed countries especially, is ageing fast and more patients are going to need treatments. Wireless sensor network (WSN) is an emerging in wireless technology for short range indoor used for health monitoring. On the other hand, the Impulse radio ultra-wideband (IR-UWB) defined by IEEE 802.15.4a standard, comes with a number of desirable features at the physical layer for wireless communications, for example, low RF power emission, ranging, accurate position location, imaging sensing radar. In this work, the potential strengths of IEEE 802.15.4a for Ambient Assisted Living Applications (AALs) has been showed. Subsequently, an IEEE 802.15.4a RF Front-End, resilient to interferers, in 65 nm CMOS for AALs has been proposed. It consists of low noise amplifier (LNA), mixer, frequency synthesizer (LO).

This paper presents a −19dBm sensitivity RF-DC converter for energy harvesting applications. It is able to harvest the energy from a dipole antenna operating at 866.5MHz (European UHF RFID frequency) providing a regulated output voltage in the range between 1.9V to 2.4V over a 2MΩ resistive load. Such voltage level is suitable to supply body sensor nodes. The four stages Dickson's RF-DC rectifier converts the UHF RF input signal to a 2V DC output, feeding the following two stages DC-DC Pelliconi's charge pump. The DC-DC charge pump, powered by a 90kHz ring oscillator, is used to further step-up the RF-DC rectifier output voltage and to realize the RF to load isolation. The output voltage regulation is performed by a feedback network made by a hysteresis comparator and a Vt-based voltage reference. The RF-DC converter shows a 38% power conversion efficiency at 0dbm input power level.

In this paper, a 4th-order low-pass continuous-time analog filter is presented, that is implemented with the cascade of two efficient and compact biquadratic cells, realized using the Super-Source-Follower topology. The biquadratic cell uses only two capacitors and four transistors: two transistors for the signal processing and two transistors as current sources for biasing pur- pose. The 4th-order filter prototype has been integrated in 0.18 μm CMOS technology. For a 33 MHz cut-off frequency, the filter per- forms 18 dBm-IIP3 for two tones at 2 MHz and 3 MHz, with total current of 770 μA from a single 1.8 V supply voltage.

61 The upgrade of the Pierre Auger Observatory required a larger number of detectors that implies a dramatic increase of the power consumption. As the analog-to-digital converter (ADC) is the most critical circuit block, an integrated solution is here proposed. A 10 b 50-MSps 5-stage pipeline ADC is implemented in 65 nm digital CMOS. It achieves 50.3 dB signal-to-noise and distortion ratio (SNDR), 52.3 dB signal-to-noise ratio (SNR), 59.2 dB spurious free dynamic range (SFDR) for a full-scale input sinewave at Nyquist frequency. The ADC features 12 mW power consumption from a 1.2 V supply, while occupying 0.8 mm2 die area. © 2014 IEEE.

In this paper a 4th-order low-pass continuous-time analog filter is presented. A smart and compact biquadratic cell has been realized using the super-source-follower circuit. The biquadratic cell synthesizes a 2nd-order low-pass transfer function, using only two capacitors and four transistors per stage: two transistors for gm-C transfer function and two transistors as current sources for biasing purpose. A 4th-order filter prototype has been integrated in CMOS 0.18μm technological node. The achieved Signal-to-Noise-Ratio is 70dB, with 8nV/√Hz in-band input referred noise. In-Band IIP3 is 18dBm. The current consumption for the entire 4th-order filter is 770μA, from a single 1.8V supply voltage.

In this paper a highly linear-dual band RF front-end (LNA and Mixer) for IR-UWB (IEEE 802.15.4a) applications is proposed. LNA exploits a common-gate (CG) stage in parallel to a common-source (CS). It performs single-ended to differential-ended operation, avoiding balun stage. It features 18 dB maximum gain, +11.8 dBm IIP3. The RF front-end receiver has been designed in 65nm CMOS technology consuming 13.5 mW. © 2014 IEEE.

Analog filters are key blocks in analog signal processing. They are widely employed in many systems, like wireless transceivers, detectors read-out, sensors interfaces, etc. The IC technology choice for such systems is mainly dictated by the requirements of high speed and low power consumption of digital circuits. This pushed an impressive movement towards scaled technology and this has important consequences on the analog circuits design. The impact of technology scaling down to nanometre scale on analog filters design is here investigated. For instance, supply voltage reduction in analog filters limits circuits design solutions and could result in higher power consumption. Moreover, at the same time, innovative systems push analog filters to get higher and higher operation frequencies, due to the increasing bandwidth/speed requirements. Recent solutions for efficient low-voltage and high frequency analog filters in nanometre technology are described. © 2014 IOP Publishing Ltd and Sissa Medialab srl.

In this paper a 4th order low-pass continuous time analog filter in CMOS 28nm technology is presented. The filter complies with the specifications of the 60GHz next-generation transceivers. A novel circuital topology is presented suitable to perform the low-pass filtering of the in-band signal, while the in-band thermal noise is high-pass filtered, improving Signal-To-Noise-Ratio. 880MHz -3dB bandwidth is obtained by a prototype of the filter simulated in 28nm CMOS technology. The overall power consumption is 4.8mW from a single 1 V supply voltage. 51dB@THD>40dBc is the SNR at 0dB gain.

This paper presents a highly linear low power fully differential downconversion mixer for impulse radio ultra wideband (IR-UWB) receivers. The downconversion mixer is designed for IR-UWB IEEE 802.15.4a standard compliant receivers. It can be reconfigured according to the selected operation channel. In fact, it enables the downconversion of the #3 mandatory channel in low band (4.4928 GHz carrier frequency, 499.2 MHz channel bandwidth), or #9 mandatory channel in high band (7.9872 GHz carrier frequency, 499.2 MHz channel bandwidth), or #11 optional channel in high band (same carrier frequency of channel #9 but 1.331 GHz channel bandwidth). Linearity of the proposed mixer is improved utilizing derivative superposition method and source degenerations at the input stage. The proposed mixer has been designed in a 65 nm CMOS technology. Post layout simulations result in 12 dBm IIP3, 16.8 dB minimum noise figure while consuming 2.7 mW from 1.2 V supply voltage. © 2013 IEEE.

In this paper a Charge-Sensitive Preamplifier (CSP) for GEM (Gas Electron Multiplier) detectors readout is presented. The CSP is responsible for signal acquisition and the conversion of the input charge into a voltage signal. The design has been realized in 0.13 μm CMOS technology. It has been demonstrated through a detailed analysis that this is the best CMOS technology to be used in this case, as regards power consumption, intrinsic gain, noise and radiation hardness. The aim is to reduce the power consumption while maintaining other performance at the state-of-the-art. The preamplifier is composed by a three-stage nested Miller Operational Amplifier, with a feed-forward compensation. The system is able to manage a 15 pF detector capacitance. The global power consumption is 1.1 mW and the Equivalent Noise Charge is 418 e-.

In this paper a dual band balun low-noise-amplifier (LNA) for impulse-radio ultra wide band (IR-UWB) applications is proposed. It exploits a common-gate (CG) stage in parallel to a common-source (CS) featuring 18 dB maximum gain

In this work we present a thermoelectric energy harvesting system consisting of a miniaturized and wearable flexible thermoelectric generator (TEG) and a dedicated ASIC, finalized to efficiently recover and manage energy from heat dispersed into the environment. The proposed TEG was realized on flexible Kapton substrate, which is particularly appreciated for its optimum properties of chemical and physical stability, permeability to atmospheric agents (humidity, oxygen) and thermal conductivity. Contrary to a conventional rigid substrate, like glass or silicon, a flexible one adds to the device lighter weight, increased robustness, freedom of shape, compactness, and low cost. Although the TEG was designed as "electronic garment" for wearable use in Ambient Assisted Living (AAL) applications, the device can be easily adapted to different contexts thanks to its flexibility and design that extend the application range to various sectors, from home automation and structural health monitoring to biotechnology. A Transfer Length Method (TLM) analysis was performed on three different multi-layer contact schemes in order to select the best solution to use for the deposition of both embedded thermometers to monitor the thermocouples junctions temperature and contact pads to electrically test single partitions of the array. A custom designed ASIC, based on step-up principle was coupled to the TEG in order to ensure a 1.2 V output and complete power management solution for wireless sensing and data acquisition.

The design of an automatic biasing system for High-Electron-Mobility-Transistors is here presented (HEMT-Biasing-System, HBS). The HBS automatically regulates the operating point of an off-chip multistage HEMT block. A proper automatic algorithm is implemented in order to maximize the HEMT transconductance (gm) efficiency (defined as gm/IDS ratio). This is an important feature in several HEMT-based systems, since they are used in LNA stages, where noise/power trade-off is a key aspect. Interfacing CMOS and HEMT technologies features several design issues, like negative gate-source voltage (to be managed by a CMOS circuits for HEMT switch-off operation) and closed-loop stability (due to the presence of very large off-chip capacitance - 100nF). The System here presented manages all these issues with tailored circuit solutions. A prototype has been designed in CMOS 0.35μm technology. It consumes 6.2mW (excluding the current consumption for HEMT driving).

This paper investigates the improvement margins in term of energy efficiency of analog filters. Starting from a landscape of analog filters presented at ISSCC until 2012, energy limits for most common analog filters architectures (Gm-C and Active-RC) are traced. Active-RC filters with reduced bandwidth requirements have larger margins of improvements compared to Gm-C. Technology scaling impact is also evaluated. Supply reduction that join the technology scaling seems to have a limited effect on Gm-C filters, as their energy limit depends on the SNR only. However, technology scaling enables larger bandwidth opamps, pushing the Active-RC technique at higher and higher frequency, where Gm-C approach generally dominates. Results have been confirmed by the detailed analysis of two of the most performing analog filters from literature.

The A-to-D converter here presented is part of a bigger system able to sense and monitor electrical/physical parameters in particles detectors, for LHC experiments. The CMOS integrated circuits operating in high-energy environments experience large leakage current and voltage/temperature variations. For this reason in LHC experiments, a proper sensing and monitoring system has been designed with the aim to provide real time information about the electrical/physical scenario for the detectors in LHC. The A-to-D converter has a resolution of 12 bits, is based on single slope architecture and is able to manage 32 input analog channels. The design is challenging for several reasons, considering the required conversion accuracy and the critical physical scenario. The entire A-to-D converter has been fully characterized with process-voltage-temperature variations, obtaining a definitive 11bit accuracy in the worst-case simulation corner. The A-to-D has been designed in CMOS 0.13 mu m technology, consumes 350 mu W (including dynamic power due to the digital circuits) and operates at 20MHz clock frequency, for a definitive 2.3kHz sample rate

This paper presents a low power transmitter for Impulse-Radio Ultra-Wideband (IR-UWB) applications. It generate short duration bi-phase modulated UWB pulses with a center frequency of 4.5 / 8 GHz according to the selected channel. A simplified transmitter architecture enabling low power consumption has been adopted. The key circuit is a phase shifter used to obtain positive and negative pulses. Generated pulses comply with requirements of the IEEE 802.15.4a standard. The transmitter is designed in 65nm CMOS technology. Simulations results show that the transmitter consumes 23 mW peak power from a 1.2V supply at 8 GHz of work frequency.

In this paper a 5th order low-pass continuous time analog filter in CMOS 45nm technology is presented. The filter design is based on a single compact cell used to synthesize five poles. The circuit performs the low-pass filtering of the in-band signal, while the in-band thermal noise is high-pass filtered, improving Signal-To-Noise-Ratio. 1-GHz -3dB-bandwidth is obtained by a prototype of the filter simulated in 45nm CMOS technology node (also Process-Voltage-Temperature simulations are available). The overall power consumption is 9mW from a single 1.2V supply voltage. 54dB@THD>40dBc is the SNR at 0dB gain.

A 10b 100-MS/s five-stage pipeline analog-to-digital converter (ADC) is implemented in 65nm digital CMOS process with power-reduction techniques for high energy physics experiments. It achieves 56.9dB signal-to-noise and distorsion ratio (SNDR), 58.5dB signal-to-noise ratio (SNR), 9.2 effective number of bits (ENOB) for a fullscale input sine at nyquist frequency. The ADC power consumption is 12.7mW from a 1.2V supply. It occupies 0.8mm(2) die area

A low power front-end for GEM (Gas Electron Multiplier) detectors has been developed in 0.13μm CMOS node. The front-end sensitivity is 0.5mV/fC which remains almost unchanged up to a 15 pF detector parasitic capacitance. The input dynamic charge range varies from 30fC to 1pC including only a single (negative) polarity charge. The front-end provides as output signal two different time-domain square-wave signals. The first one indicates the charge detection event and the second one the amount of charge (providing a time-domain impulse, whose duty-cycle is proportional to the effective charge read by the front-end). Proper automatic calibration circuits are then implemented in order to optimize the front-end performance in case of CMOS process and temperature variations. The power consumption is 3.8mW, against 12mW in the existing market solutions [9]. A feed-forward opamp architecture has been exploited in analog part of read-out channel, in order to improve speed and time-response slope.

We present a 60 GHz four-antenna phased-array direct conversion receiver in 90 nm RF CMOS with an LO based on subharmonic injection locking, beamforming that is partially in the LO path and partially at analog baseband, and an analog baseband section. The LO system features a set of four 60 GHz oscillators, locked to the fifth harmonic of a central oscillator, improving the phase noise performance and robustness. Phase shifting is realized in two steps and two domains, which reduces the complexity of phase shifters and signal degradation at analog baseband. Signal combination is performed at analog baseband, followed by a variable-gain amplifier and a baseband filter, which together allow for 6-th order filtering with 880 MHz bandwidth and 20 dB of gain adjustment with 1 dB steps. The system provides a maximum conversion gain of 42 dB with a total power consumption of 450mW and chip area of 3.15 by 1.9 mm².

In this paper the complete design of a Programmable Gain Amplifier embedded in UWB receiver is presented. The receiver is part of a System-On-Chip placed inside the car tire (with the aim to interchange data with the car control unit) where dynamic stress, temperature and aging are very important issues, resulting in severe design constraints for CMOS analog integrated circuits. Furthermore, the SoC is biased by vibration-based energy scavenger, and a as consequence, very low power is available for the integrated circuits. High input impedance is required from system level constraints and this is achieved with MOS input devices, exploiting dual differential input Opamp. The PGA gain is programmable in the 15dB-to-50dB range with 1dB step. For the maximum gain level (50dB), the Input-Referred-Noise power spectral density is lower than 20nV/vHz. From a single 1V supply, for the minimum gain level (15dB), a 0.8Vzero-peak output signal is processed with THD=−40dBc.

In this paper a digital amplitude modulator for a polar transmitter is presented. The instantaneous output power is modulated by adjusting the amplifiers load through a digitally controlled impedance transformation network. The modulator is suited for modulation schemes with moderate peak-to-average power ratio (PAPR), such as π/4 DQPSK. The modulator may also be used for fine gain control in constant envelope modulation schemes. A class E amplifier with digital impedance amplitude modulation is integrated in 90 nm CMOS. It achieves a peak output power of 9 dBm with a PAE of 30% when powered from a 1.2 V supply. The measured EVM is 2.6% for a 6 dBm π/4 DQPSK modulated signal with 2 Mb/s signal rate at 2.4 GHz RF frequency. © 2004-2012 IEEE.

A 90 nm-CMOS power-optimized analog baseband chain for ultra-low-power impulse-radio ultra-wideband (IR-UWB) receivers is presented. The proposed device merges the functions of a programmable gain amplifier (PGA) and a low-pass filter (LPF). It consists of the cascade of three biquadratic cells made up by opamps in a series-shunt configuration, which features high input impedance, low load effects in the cascade blocks, and better frequency response. The opamp parameters are included in the overall biquad transfer function. This allows getting very low power performance, since the opamp bandwidth is not required to be much larger than the filter cutoff frequency. Moreover, the current consumption is optimized according to the selected gain level (1.3 mA at 0 dB-gain up to 1.9 mA at 40 dB-gain). The PGA features a 0-40 dB programmable gain range with a 5 dB gain-step. The LPF performs a sixth-order 255 MHz low-pass frequency response. For the overall chain the IIP3 is 14 dBm at 0 dB gain, while the input referred noise is 12.5 nV/√Hz at 40 dB gain. © 2012 IEEE.

We present the bidirectional power line communication system developed in parallel to an electronic board for driving and control of HID (high-intensity discharge) and LED (light-emitting diode) lamps. The communication system, developed to be applied in the sector of public illumination, is been designed to combine high efficiency and reliability with low production costs; it consists indeed of discrete cheap components. The communication system described in this paper implements the technique of transporting digital information over existing power lines, avoiding the issue of installing new cables. Digitized signals can use power line cables through the amplitude voltage and current modulation. The solution proposed is more advantageous compared to communication techniques currently on the market which are essentially two types, power line carrier (modem for high-voltage lines) or radio (zig-Bee transceiver). Copyright © 2012 P. Visconti et al.

In this work a new concept of hybrid lamps burner is presented. The High Intensity Discharge (HID) lamps and the new generation Light Emitting Diodes (LED) lamps can be driven by the same electronic ballast using this hybrid ASIC in 0.35m CMOS technology. In the state-of-art the electronic ballasts are managed by powerful general-purpose devices (usually FPGA or microcontroller). These devices are not customized for the specific application. Thus they have a larger area occupation and power consumption compared to ASIC solution. The designed ASIC power consumption is 35 mW and the package area is about 6.5 cm2 against 550 mW and 6.5 cm2 for commonly used PIC 18FXX2. © 2011 IEEE.