Search

This letter presents a CMOS reverse received signal strength indicator (reverse-RSSI) based logarithmic power detector (PD). A capacitor attenuation array and unbalanced source-coupled rectifiers are utilized to constitute the reverse-RSSI architecture, which greatly increases the maximum detectable power. Two auxiliary capacitors in the rectifier are introduced to improve linearity at high input power dramatically. The PD with 0.4–5-GHz operating frequency can be fully integrated and has stable and reliable performance according to multiple tests. Measurement results show that the maximum detectable power achieves +35 dBm and dynamic range reaches 45 dB with ±1-dB linearity error. The proposed PD is implemented in a standard 180-nm CMOS process with 0.085 mm2 core area. The total static power consumption is 0.78 mW with a 3.3-V supply voltage.

A fully CMOS integrated low TX noise UHF RFID digital transmitter with tunable directional coupler is proposed. The transmitter decreases the AM noise density to −144.6 dBc/Hz at 10 kHz offset by eliminating noisy conventional analog components and optimizing LO chain. The tunable transformer-based directional coupler which is feasible for CMOS integration exhibits high isolation performance of −55 dB over the entire band. The transmitter with quadrature DPA structure supports DSB/SSB/PR-ASK modulation, and with the directional coupler, it achieves 22.8 dBm peak power with drain efficiency of 37.8%. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1750–1756, 2016

This paper proposes a 2.4-GHz pre-bias RF energy harvesting rectifier with -35-dBm sensitivity for self-powered chips of wireless sensor networks (WSNs) for Internet of Things (IoT) applications. For high sensitivity, a pre-bias topology is presented by designing pre-stage and drive-stage rectifiers separately with multiple antennas. The pre-stage and the bias circuit just provide a proper bias voltage without driving loads. At single drive-stage configuration, -35-dBm sensitivity can be achieved with 2.4-GHz RF input power, 10-MΩ output load and 0.5-V continuous output voltage. When an 1% duty-cycled operating mode is adopted, 25-μW power can be supplied intermittently with 0.5-V output voltage. This proposed circuit is designed in 0.18-μm standard CMOS process.

This paper presents a temperature and supply voltage variation-tolerant CMOS relaxation oscillator which is suitable for ultra-low power systems. A low-power low-cost half-period pre-charge compensation scheme is proposed to eliminate influences of the delay of the comparator and the RS latch on the frequency stability of the relaxation oscillator. In a clock period consisting of four working stages including normal charge, discharge, pre-charge and hold stage, the threshold voltage of comparators is adjusted dynamically. A 32.7-kHz relaxation oscillator with the proposed half-period pre-charge compensation scheme is implemented in a TSMC 0.18-μm CMOS process, occupying a silicon area of 0.048 mm2. Simulation results show that the proposed relaxation oscillator consumes 51-nW at room temperature from 0.6-V power supply, and temperature stability of 43.1 ppm/°C from −55 °C to 125 °C and ±0.60% frequency variation with supply voltage from 0.5 V to 1.0 V are achieved.

This paper proposes a DC-DC buck converter with all-pass network based passive level shifter in 55nm standard CMOS process, for battery powered portable applications. In order to handle high battery voltages in this advanced standard CMOS process, a passive level shifter based on all-pass network is applied for gate oxide protection. Drain extension is proposed to obtain high breakdown voltage of active region. The proposed buck converter with the passive level shifter works in DCM operation as its load current varies from 0.1–10mA. The buck converter achieves a peak efficiency of 93.7% and 83.8% at 10mA load current, with a supply voltage of 1.8V and 3.7V, respectively.

An ultra low power digital baseband processor for passive UHF RFID tag which is compatible with the protocol of Chinese local standard (840–845 MHz and 920–925 MHz) is presented in this paper. A highly reused register bank and a low-cost sort algorithm are proposed to minimize the power consumption and several other low power techniques are adopted, including low supply voltage, clock gating, and minimum operation frequency. The processor is fabricated in SMIC 0.18 um standard CMOS process and consumes 358 nA at 0.6 V voltage supply according to measured results and occupies only 0.1 mm2 area.

A wide band radio frequency (RF) root-mean-square (RMS) power detector (PD) is presented in this paper. A CMOS rectifier with unbalanced source-coupled pairs and auxiliary capacitors is utilized to constitute the reverse received signal strength indicator (reverse-RSSI) architecture as proposed power detector with operating frequency from 300 MHz to 10 GHz. The auxiliary capacitors are introduced to improve linearity at high input power dramatically. The power detector can be connected to power amplifier without directional coupler due to the capacitor attenuation array. Simulation results show that the maximum detection power is as high as +30 dBm and dynamic range reaches more than 42 dB with ±1 dB error. The proposed power detector is implemented in a standard 180nm CMOS process with 0.113 mm2 core area. The supply voltage is 3.3 V, and its static power consumption is 0.55 mW.

A novel human body channel (HBC) energy harvesting scheme for body sensor networks (BSNs) is proposed in this paper. Human body channel is utilized innovatively as energy transmission medium to reduce the transmission loss dramatically and eliminate influence of shadow effect. Further, a high sensitivity and efficiency rectifier is presented by introducing an effective threshold compensation circuit. Experimental results of the energy harvesting scheme show that it can supply 2-μW power typically at −5 dBm transmitted power and up to 19.5-μW at +7 dBm transmitted power by 30 cm distance of human body channel. The sensitivity of the proposed rectifier is −22.5 dBm with 1-V output voltage. When offering 5-μA output current, the rectifier can achieve 25.87% efficiency. The rectifier is implemented in a standard 0.18-μm CMOS process and operating frequency is 145 MHz.

This paper presents a 0.5–2GHz RF front-end with Series N-path Filter. With series 8-path filter applied, an ultimate rejection larger than 46 dB with 30 dB out-of-band rejection at 50 MHz offset is achieved. Dynamic power consumption is saved due to small filter switch size compared with parallel structures. Utilizing a tunable narrow band LNA in front of series N-path filter, 3rd harmonic rejection exceeding 54 dB with robust to process variation is realized. These techniques improve the front-end's adjacent and far-end frequency selectivity in RF domain, relaxing mixer's linearity design pressure. Implemented in 65 nm CMOS process, the frontend achieves a NF of 2.6–5.7 dB and maximum gain of 46–60 dB at 0.5–2 GHz, consuming 18–26 mW from 1.2 V voltage supply and occupies an area of 0.56 mm2.

This letter proposes a miniature CMOS stacked spiral-coupled (SSC) directional coupler for a fully integrated CMOS transceiver to isolate the large transmit power from the transmitter to the receiver. It consists of two 90 °-rotated center-aligned SSC coils. The path center of one coil is aligned to the gap center of the other coil. The grounded secondary coil plays a role of ground shielding for reducing the insertion loss. Two capacitors are utilized for tuning the center frequency and isolation level. Fabricated in a standard CMOS process, it achieves an isolation of -67 dB, an insertion loss of -0.8 dB, and a coupling of -16.1 dB and only occupies 0.3×0.3 mm2 of silicon area. To the authors' knowledge, this is the first CMOS directional coupler at the UHF band, with the smallest form factor when compared with other implementations of directional couplers.

This paper presents a SAW-less GNSS front-end amplifier with GSM blocker suppression using CMOS directional coupler notch filter. The front-end amplifier is aimed at the GNSS receiver integrated in cellular phones. Based on our proposed CMOS stacked spiral-coupled (SSC) directional coupler working at the frequency of 900MHz as notch filter, the front end amplifier achieves a NF of 1.7dB and a 80.4-dB suppression of the GSM blocker while provides signal gain of 38.6-dB for the GPS L1-band signal.