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Up to 820 kW of rf power is delivered to the only 460 cm 2 area of antennae with the radiation resistance about 1 ω. The radiation resistance agrees well with the strong damping model proposed by J. Adam. A plan for ridge wave guide coupling in JFT-2M is also shown.

Sustainability in electronics has a growing importance due to, e.g. increasing electronic waste, and global and European sustainability goals. Printing technologies and use of paper as a substrate enable manufacturing of sustainable electronic devices for emerging applications, such as the multi-layer anti-counterfeit label presented in this paper. This device consisted of electrochromic display (ECD) element, NFC (near field communication) tag and circuitry, all fully roll-to-roll (R2R) printed and assembled on plastic-free paper substrate, thus leading to a sustainable and recyclable device. Our setup uses harvested energy from HF field of a smartphone or reader, to switch an electrochromic display after rectification to prove authenticity of a product. Our novelty is in upscaling the manufacturing process to be fully printable and R2R processable in high-throughput conditions simulating industrial environment, i.e. in pilot scale. The printing workflow consisted of 11 R2R printed layers, all done in sufficient quality and registration. The printed antennas showed sheet resistance values of 32.9±1.9 mΩ/sq. The final yield was almost 1500 fully printed devices, and in R2R assembly over 1400 labels were integrated with 96.5% yield. All the assembled tags were readable with mobile phone NFC reader. The optical contrast (ΔE*) measured for the ECDs was over 15 for all the printed displays, a progressive switching time with a colour change visible in less than 5 s. The smart tag is ITO-free, plastic-free, fully printed in R2R and has a good stability over 50 cycles and reversible colour change from light to dark blue.

Analysis results of autodyne signals of the double-diode oscillator, which is under influence of the proper reflected emission from the moving object, are presented. The analysis is performed on the base of the autodyne mathematical model presented in the form of a system of two mutually-locked partial oscillators under condition of strong mutual coupling. Peculiarities of signal formation are considered for various parameters of partial oscillators and coupling conditions. Experimental data are obtained for the 8mm-range Gunn double-diode oscillator of the flange type.

Analysis results of coupling degree influence of the autodyne oscillator with an antenna are presented together with influence of the impedance characteristic type (soft or rigid) of the active element on the coefficients of autodyne amplification, autodyne frequency deviation and power transfer as well as on the noise parameters and characteristics. Analytical and numerical calculations of above-mentioned parameters and characteristics are performed, and results of experimental investigations of the 8mm-range Gunn diode autodyne are given.

Scaling of bulk MOSFET faces great challenges in nanoscale integration technology by producing short channel effect which leads to increased leakage. FinFET has become the most promising substitute to bulk CMOS technology because of reducing short channel effect. Dual-gate FinFET can be designed either by shorting gates on either side for better performance or both gates can be controlled independently to reduce the leakage and hence power consumption. A six transistor SRAM cell based on independent-gate FinFET technology is described in this paper for simultaneously reducing the active and standby mode power consumption. A work is focused on the independent gate FinFET technology as this mode provides less power consumption, less area consumption and low delay as compared to other modes. Leakage current and power consumption in independent gate FinFET is compared with tied gate or shorted gate FinFET SRAM cell. Moreover, delay has been estimated in presented SRAM cells. Further, leakage reduction technique is applied to independent gate FinFET 6T SRAM cell.

This paper presents three transistors (3T) based Dynamic Random Access Memory (DRAM) cell in which noise, static power, and data retention voltage (DRV) have been reduced. The spesified parameters in the proposed eDRAM gain cell were improved by connecting the source of storage device to the read word line signal instead of supply voltage. As we all know, power consumption plays a vital role in VLSI design and thus, it is enumerated among the top challenges for the semiconductor chip industries. With the intention to maintain the performance of write operation, we diminish DRV and increase the read margin of eDRAM cell with our designed circuit which is introduced as “A Boosted 3T eDRAM gain cell”. It is a kind of eDRAM cell that utilizes a read word line (RWL) via three PMOS transistors instead of NMOS transistors. PMOS devices are preferred as they have radically less gate leakage current, which confer better results for data retention and thus, boost up the read margin of the cell. Simulation results have been obtained by using Cadence Virtuoso Tool at 45 nm technology for the proposed model. Based on simulation results we can conclude that the parameters of the proposed eDRAM gain cell essentially improved as compared with convertional eDRAM gain cell and the achieved parameters are as follows: static power is 0.767 pW, DRV is 142.009 mV and noise is 8.421 nV/Hz1/2.