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As an important constraint on the threshold voltage (Vt) distribution, the random telegraph noise (RTN) has attracted much attention due to the widely used multi-bit-per-cell technology in 3D NAND flash. This work investigated the physical mechanisms of RTN in charge- trap-based 3D NAND flash. According to statistical 3D TCAD simulation analysis, the fringing field from the control gate and the random discrete nitride trapped charges, two competitive mechanisms, are proposed to be responsible for the non-monotonic RTN behavior. As the programmed cell Vt level increases, the increasing fringing field from the control gate reduces the current-path percolation effect and the RTN amplitude. However, once the random discrete nitride trapped charges start to dominate the percolation current path, the RTN amplitude increases significantly. Instructively, the clarification of RTN competitive mechanisms contributes to compacting Vt distributions specifically in multi-level 3D NAND flash. [ABSTRACT FROM AUTHOR]

The detection of temporal correlations among event-driven data streams is widely demanded in data-intensive applications such as edge computing. In this work, temporal correlation detection is enabled by the combination of 3D NAND flash and in-memory computing. Different from mathematical scheme by covariance matrix calculation, here the detection is implemented by exploiting the physical process of charge tunneling and accumulation. Thus the intrinsic charge-trapping dynamics in 3D NAND flash can be leveraged to perform in-memory computing. The computing results are stored and imprinted in the threshold voltages of the 3D NAND device array, enabling co-existence of computation and storage in the same devices. On this basis, the validation of temporal correlation detection further paves the way for 3D NAND application in high-level non-von Neumann computing. [ABSTRACT FROM AUTHOR]

3D NAND Flash with high storage capacity is in great demand for several technologies, which requires high performance and good reliability at the same time. Therefore, it is proposed to adjust the tunnel layer by changing the first SiO2 (O1) layer thickness near poly Si channel in the tunnel layer based on SiO2/SiOxNy/SiO2 structure. The optimal thickness of O1 layer is found. Under the optimal condition, program speed increased by 19% compared with no O1 layer deposition, though erase speed is slightly decreased by about 7%, the initial threshold voltage shift is improved greatly. Experimental results demonstrate that there are complex mechanisms affected by the dielectric constant, band barrier and equivalent oxide thickness. The optimization of O1 layer is useful towards an understanding of program/erase speed and retention characteristics. [ABSTRACT FROM AUTHOR]

The mechanisms and characteristics of program noise (PN) in charge trap based 3D NAND flash memory are investigated in this work. Electron injection statistics is found to be primarily responsible for PN. Moreover, it is found that PN gets worse after program and erase (PE) cycling in 3D charge trapping memory devices. A physical model is proposed to explain the observations. After heavy cycling stress, new traps are generated in the tunnel oxide, and more charges can be trapped. As a result, program speed increases and charge centroid shifts towards the tunnel oxide, which lead to worse PN. Furthermore, the upper part of Vt distribution is broadened after heavy PE cycling. The contribution of the worse PN to the upper part broadening after cycling is studied through Monte Carlo simulation. [ABSTRACT FROM AUTHOR]

On 12-in wafers of 65-nm-node floating gate NOR flash memory, charge pumping measurements show that compared to those on the edge dies (type A), the devices on the central dies (type B) have more severe damage in the source (S) and drain (D) regions. In type-B devices, the worse damage is due to the generation of interface traps in the S/channel overlapping region and the generation of bulk traps in the S and D junction region. In type-A devices, the damage is much weaker. The generation of interface traps is observed in the S/channel overlapping region. However, it is hardly measurable on the D side. The endurance characteristics have been measured in these two kinds of devices under the channel hot electron program and Fowler–Nordheim erase. In type-B devices, after program/erase cycling the memory window closure is more serious and the junction leakage also degrades greatly with the generation of a lot of bulk traps at S and D regions. The damage in fresh devices is suggested to be due to the plasma etching processes. [ABSTRACT FROM PUBLISHER]

In this letter, the retention properties of charge trapping memory with decreased thickness of ultra-thin HfO2 charge trapping layer are investigated by Kelvin probe force microscopy (KFM) technology. Experiment results show that retention properties became worse with the reducing of HfO2 thickness and increasing of temperature. Based on total remaining charge density and lateral leakage charge density extracted from the contact potential differences, we find that vertical charge leakage acted as a dominant role of charge loss with respect to lateral charge redistribution. Furthermore, effective trap energies are extracted from KFM analysis at high temperatures and it is concluded that the suppression of lateral charge redistribution in thinner HfO2 layer results from deeper trap energies. [ABSTRACT FROM PUBLISHER]