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We present a methodology and the corresponding experimental results to identify the exact location of the traps that induce hot electron trapping in AlGaN/GaN heterostructures grown on Si substrates. The methodology is based on a combination of lateral and vertical electrical stress measurements employing three ohmic terminals on the test sample structure with different GaN buffer designs. By monitoring the evolution of the lateral current during lateral as well as vertical stress application, we investigate the trapping/detrapping behaviors of the hot electrons and identify that the traps correlated with current degradation are in fact located in the GaN buffer layers. The trap activation energies (0.38-0.39 eV and 0.57-0.59 eV) extracted from either lateral or vertical stress measurements are in good agreement with each other, also confirming the identification. By further comparing the trapping behaviors in two samples with different growth conditions of an unintentionally doped GaN layer, we conclude that the traps are most likely in the unintentionally doped GaN layer but of different origins. It is suggested that the 0.38-0.39 eV trap is related to residual carbon incorporation while the 0.57-0.59 eV trap is correlated with native defects or complexes. [ABSTRACT FROM AUTHOR]

We report the interface characterization of Al2O3/AlN/GaN MOS (metal-oxide-semiconductor) structures with an AlN interfacial layer. A thin monocrystal-like interfacial layer (AlN) is formed at the Al2O3/GaN to effectively block oxygen from the GaN surface and prevent the formation of detrimental Ga-O bonds. The suppression of Ga-O bonds is validated by X-ray photoelectron spectroscopy of the critical interface. Frequency-dispersion in C-V characteristics has been significantly reduced, owing to improved interface quality. Furthermore, using the conventional conductance method suitable for extracting the interface trap density Dit in MOS structures, Dit in the device with AlN was determined to be in the range of 1011-1012eV-1cm-2, showing one order of magnitude lower than that without AlN. Border traps near the gate-dielectric/GaN interface were identified and shown to be suppressed by the AlN interfacial layer as well. [ABSTRACT FROM AUTHOR]