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Positive bias temperature instability (PBTI) is poised to cause significant degradation to nFETs with deep scaling into nanometers. It is commonly modeled by a power law fitted with measured threshold voltage shift. For the first time, this paper shows that such models do not warrant PBTI prediction outside the stress conditions used for the fitting. The underlying cause for this failure is the errors in the extracted power exponent. Based on the understanding of different types of defects, we develop a robust as-grown-generation model and demonstrate its capability for accurate prediction of PBTI under both dc and ac conditions. The generation-induced degradation is found to play a key role. Analysis reveals that although PBTI is usually smaller than negative BTI (NBTI) within the typical test time window, it can exceed NBTI by the end of device lifetime. [ABSTRACT FROM AUTHOR]

Resistive-switching random access memory (RRAM) is widely considered as a disruptive technology. Despite tremendous efforts in theoretical modeling and physical analysis, details of how the conductive filament (CF) in metal-oxide-based filamentary RRAM devices is modified during normal device operations remain speculative, because direct experimental evidence at defect level has been missing. In this paper, a random-telegraph-signal-based defect-tracking technique (RDT) is developed for probing the location and movements of individual defects and their statistical spatial and energy characteristics in the CF of state-of-the-art hafnium-oxide RRAM devices. For the first time, the critical filament region of the CF is experimentally identified, which is located near, but not at, the bottom electrode with a length of nanometer scale. We demonstrate with the RDT technique that the modification of this key constriction region by defect movements can be observed and correlated with switching operation conditions, providing insight into the resistive switching mechanism. [ABSTRACT FROM PUBLISHER]

The access transistor of SRAM can suffer both positive bias temperature instability (PBTI) and hot carrier aging (HCA) during operation. The understanding of electron traps (ETs) is still incomplete and there is little information on their similarity and differences under these two stress modes. The key objective of this paper is to investigate ETs in terms of energy distribution, charging and discharging properties, and generation. We found that both PBTI and HCA can charge ETs which center at 1.4 eV below conduction band ( Ec ) of high-k dielectric, agreeing with theoretical calculation. For the first time, clear evidences are presented that HCA generates new ETs, which do not exist when stressed by PBTI. When charged, the generated ETs’ peak is 0.2 eV deeper than that of preexisting ETs. In contrast with the power law kinetics for charging the preexisting ETs, filling the generated ETs saturates in seconds, even under an operation bias of 0.9 V. ET generation shortens device lifetime and must be included in modeling HCA. A cyclic and antineutralization ETs model is proposed to explain PBTI and HCA degradation, which consists of preexisting cyclic ETs, generated cyclic ETs, and antineutralization ETs. [ABSTRACT FROM AUTHOR]

Continuing CMOS performance scaling requires developing MOSFETs of high-mobility semiconductors and InGaAs is a strong candidate for n-channel. InGaAs MOSFETs, however, suffer from high densities of border traps, and their origin and impact on device characteristics are poorly understood at present. In this paper, the border traps in nMOSFETs with an In0.53Ga0.47As channel and Al2O3 gate oxide are investigated using the discharging-based energy profiling technique. By analyzing the trap energy distributions after charging under different gate biases, two types of border traps together with their energy distributions are identified. Their different dependences on temperature and charging time support that they have different physical origins. The impact of channel thickness on them is also discussed. Identifying and understanding these different types of border traps can assist in the future process optimization. Moreover, border trap study can yield crucial information for long-term reliability modeling and device time-to-failure projection. [ABSTRACT FROM AUTHOR]

High density of electron trapping in high- \kappa intergate dielectric (IGD) materials remains a major concern for planar memory cells with either poly-Si or hybrid floating gates (FGs). In this paper, for the first time, using the ultrafast I{-}V measurements, it is demonstrated that a significant portion of the P/E windows are actually contributed by electrons trapped initially in the high- \kappa$ IGD stacks during program/erase, and then discharged to FG or control gate during verification. More importantly, it is demonstrated, for the first time, that this fast charge transition can be suppressed using novel multilayer high- $\kappa$ IGD structures, and the fast window instability can be eliminated. [ABSTRACT FROM PUBLISHER]

High-\kappa stacks have been used in the 20-nm generation of floating gate (FG) flash memory cells as the interpoly dielectric (IPD). However, electron trapping in high-\kappa materials remains a major concern for the further development of FG technology. For conventional FG cells, read/pass disturbance in the erased states is a major issue. In this paper, for the first time, it is observed that electron trapping/detrapping in the high-\kappa IPD layers can cause severe abnormal read/pass disturbances in the programmed states. Extensive evidence shows that this instability in programmed states originates from several competing mechanisms, including the redistribution of electron trapping between the IPD and FG and the electron discharging from FG/IPD into the control gate. This issue should be addressed in the development of future generations of FG Flash technology with higher-\kappa IPD materials. [ABSTRACT FROM PUBLISHER]

Endurance is one of the key criteria for Flash memory technologies, particularly for the generations beyond 30 nm with high-\kappa materials. It is observed in this paper that the electron trapping in high-\kappa layers causes threshold-voltage window closure under dynamic program/erase cycling operations. This closure does not originate from the generation of new traps or from further trapping of electrons injected from the gate during erasing. By utilizing a recently developed multipulse technique, it is found that the energy distribution of the electron trapping in the high-\kappa layer significantly changes after cycling. Electron trapping at the deeper energy levels continuously increases as cycling proceeds, because it does not reach saturation within one programming pulse. The trapping in deep levels cannot be discharged under typical erase conditions, and an increase in deep-level trapping also causes a reduction of trapping at shallow levels. It is concluded that the window closure observed in this paper is caused by a combination of increased deep trapping after erasing and a reduction of shallow trapping after programming. [ABSTRACT FROM PUBLISHER]

A new discharge-based multipulse technique has been developed in this paper, which overcomes the shortcomings of the existing techniques, such as the charge pumping, charge injection and sensing, and two-pulse C–V techniques. It captures the energy signature for electron traps across high- \kappa materials and can be a useful tool for material selection during technology development. Trap distributions in \HfO2, \Al2\O3, and HfAlO have been compared to identify the effects of material variation. It is observed that hafnium gives the shallow traps at about 0.45 eV above the silicon conduction band bottom (Si ECB), and the deep traps at 0.8 eV below the Si ECB are caused by aluminum. HfAlO combines the features in \HfO2 and \Al2\O3. A peak near the Si ECB has been observed in all the three materials. [ABSTRACT FROM PUBLISHER]