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High density of electron trapping in high- \kappa intergate dielectric (IGD) materials remains a major concern for planar memory cells with either poly-Si or hybrid floating gates (FGs). In this paper, for the first time, using the ultrafast I{-}V measurements, it is demonstrated that a significant portion of the P/E windows are actually contributed by electrons trapped initially in the high- \kappa$ IGD stacks during program/erase, and then discharged to FG or control gate during verification. More importantly, it is demonstrated, for the first time, that this fast charge transition can be suppressed using novel multilayer high- $\kappa$ IGD structures, and the fast window instability can be eliminated. [ABSTRACT FROM PUBLISHER]

High-\kappa stacks have been used in the 20-nm generation of floating gate (FG) flash memory cells as the interpoly dielectric (IPD). However, electron trapping in high-\kappa materials remains a major concern for the further development of FG technology. For conventional FG cells, read/pass disturbance in the erased states is a major issue. In this paper, for the first time, it is observed that electron trapping/detrapping in the high-\kappa IPD layers can cause severe abnormal read/pass disturbances in the programmed states. Extensive evidence shows that this instability in programmed states originates from several competing mechanisms, including the redistribution of electron trapping between the IPD and FG and the electron discharging from FG/IPD into the control gate. This issue should be addressed in the development of future generations of FG Flash technology with higher-\kappa IPD materials. [ABSTRACT FROM PUBLISHER]

We investigate and quantify the role played by electrons and holes during the erase operation of TANOS memories by means of charge separation experiments and physics-based simulations. Results demonstrate that electron emission via trap-to-band tunneling dominates the first part of the erase operation, whereas hole injection prevails in the remaining part of the transient. In addition, we show that the efficiency of the erase operation is high and constant mainly because of the high energy offset between nitride and alumina valence bands. Our results clearly identify the physical mechanisms responsible for TANOS erase and allow deriving some important guidelines for the optimization of this operation. [ABSTRACT FROM PUBLISHER]

Endurance is one of the key criteria for Flash memory technologies, particularly for the generations beyond 30 nm with high-\kappa materials. It is observed in this paper that the electron trapping in high-\kappa layers causes threshold-voltage window closure under dynamic program/erase cycling operations. This closure does not originate from the generation of new traps or from further trapping of electrons injected from the gate during erasing. By utilizing a recently developed multipulse technique, it is found that the energy distribution of the electron trapping in the high-\kappa layer significantly changes after cycling. Electron trapping at the deeper energy levels continuously increases as cycling proceeds, because it does not reach saturation within one programming pulse. The trapping in deep levels cannot be discharged under typical erase conditions, and an increase in deep-level trapping also causes a reduction of trapping at shallow levels. It is concluded that the window closure observed in this paper is caused by a combination of increased deep trapping after erasing and a reduction of shallow trapping after programming. [ABSTRACT FROM PUBLISHER]

A fast response technique is developed to investigate the short-term postprogram and post-erase discharge in Flash memory devices. The procedure is based on fast VTH -evaluation methods developed for bias temperature instability and provides the transient characteristics after 20 ms under the program or erase conditions. The following different structures are investigated: 1) \SiO2/high-k stacks; 2) charge trap memories; 3) and floating gate memories. Dielectrics targeted for Flash memory applications are used as charge trap layers and interpoly dielectrics. In this paper, we show results on \Al2\O3, DyScO, GdScO, and hexagonal and perovskite LuAlO. The postprogram and post-erase curves hold useful information about the dielectric properties and are used as a fast screening technique for alternative materials. [ABSTRACT FROM PUBLISHER]

The operation and reliability of nonvolatile memory concepts based on charge storage in nitride layers, such as TANOS (\TaN/Al2\O3/\Si3\N4/ \SiO2/\Si), require detailed information on the energy and spatial distribution of the charge defects in both the nitride and the \Al2\O3 blocking dielectric. This paper focuses on the characterization of \Al2\O3. We have successfully applied complementary trap characterization techniques to crystalline \gamma-phase- \Al2\O3 in order to obtain a complete picture of the spatial and energetic distribution of the defect density. As a result, two defect types at energy levels 1.8 and 3.5 eV below the conduction band edge are found. [ABSTRACT FROM PUBLISHER]

A new discharge-based multipulse technique has been developed in this paper, which overcomes the shortcomings of the existing techniques, such as the charge pumping, charge injection and sensing, and two-pulse C–V techniques. It captures the energy signature for electron traps across high- \kappa materials and can be a useful tool for material selection during technology development. Trap distributions in \HfO2, \Al2\O3, and HfAlO have been compared to identify the effects of material variation. It is observed that hafnium gives the shallow traps at about 0.45 eV above the silicon conduction band bottom (Si ECB), and the deep traps at 0.8 eV below the Si ECB are caused by aluminum. HfAlO combines the features in \HfO2 and \Al2\O3. A peak near the Si ECB has been observed in all the three materials. [ABSTRACT FROM PUBLISHER]