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A class-AB OTA (operational transconductance amplifier) topology with rail-to-rail input common-mode range is proposed for application in very low-voltage applications. High efficiency is achieved by reusing transistors both for class-AB operation and for mirroring the output currents, and a threshold lowering technique is applied to allow supply voltages less than two threshold voltages. Simulations in 40 nm CMOS technology show 41 dB gain at ±0.3 V supply voltage, a unity-gain frequency of 8.8 MHz on a 5 pF load, class-AB behaviour and full rail-to-rail operation when closed in unity-gain buffer configuration. [ABSTRACT FROM AUTHOR]

A biasing technique for minimum supply CMOS amplifiers is proposed. The bulk terminals of the input transistors of a pseudo-differential amplifier are exploited in a switched-capacitor control loop to set the quiescent current. Simulations on a design powered with 0.7 V show that the performance obtained is comparable to that of a traditional differential pair supplied with 1 V. [ABSTRACT FROM AUTHOR]

We present a low voltage low power architecture for an integrated current conveyor (CCII) topology, designed to decrease the stand-by power dissipation without affecting the CCII transient performance. In the proposed circuit, implemented in a standard AMS 0.35 um CMOS technology, an extra current flows into the circuit only when an input voltage variation occurs (through the adaptive biasing technique), so improving the transient response speed without a substantial increase of the average power consumption. Simulation results confirm the expected theoretical considerations. [ABSTRACT FROM AUTHOR]