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In this paper, we present a postsilicon-tuning technique to improve parametric yield of SRAM array using body bias (BB). First, we show that, although parametric failures in SRAM are due to local random intradie variations, the parametric failures increase at extreme interdie corners. Next, we show that proper BB can reduce different types of parametric failures. Finally, we show that adaptive application of BB to different dies, based on their interdie corners, reduces the total number of parametric failures in those dies. This helps to repair the faulty dies at different interdie corners, thereby improving SRAM yield. We show that postsilicon-tuning using BB can result in significant yield enhancement for SRAM (8%-25% in predictive 70-nm technology). [ABSTRACT FROM AUTHOR]

In nanoscale complementary metal-oxide-semiconductor (CMOS) devices, a significant increase in subthreshold, gate, and reverse-biased junction band-to-band-tunneling (BTBT) leakage results in large leakage power in logic circuits. Leakage components interact with each other at the device level (through device geometry and the doping profile) and at the circuit level (through the node voltages). Due to the circuit-level interaction of the different leakage components, the leakage of a logic gate depends on the circuit topology, i.e., the number and the nature of the other logic gates connected to its input and output. In this paper, the effect of loading on a leakage of a circuit is analyzed for the first time. The authors have also proposed a method to accurately estimate the total leakage in a logic circuit from its logic-level description considering the impact of loading and transistor stacking. [ABSTRACT FROM AUTHOR]

Dramatic increase of subthreshold, gate and reverse biased junction band-to-band-tunneling (BTBT) leakage in scaled devices results in the drastic increase of total leakage power in a logic circuit In this paper, a methodology for accurate estimation of the total leakage in a logic circuit based on the compact modeling of the different leakage current in nanoscaled bulk CMOS devices has been developed. Current models have been developed based on the device geometry, two-dimensional doping profile, and operating temperature. A circuit-level model of junction BTBT leakage has been developed. Simple models of the subthreshold current and the gate current have been presented. Also, the impact of quantum mechanical behavior of substrate electrons, on the circuit leakage has been analyzed. Using the compact current model, a transistor has been modeled as a stun of current sources (SCS). The SCS transistor model has been used to estimate the total leakage in simple logic gates and complex logic circuits (designed with transistors of 25-nm effective length) at room and elevated temperatures. [ABSTRACT FROM AUTHOR]

Carbon nanotube field-effect transistors (CNFETs) are being extensively studied as possible successors to CMOS. Novel device structures have been fabricated and device slmulators have been developed to estimate their performance in a sub-10-nm transistor era. This paper presents a novel method of circuit-compatible modeling of single-walled semiconducting CNFETs in their ultimate performance limit, For the first time, both the I-V and the CV characteristics of the device have been efficiently modeled for circuit simulations. The model so developed has been used to simulate arithmetic and logic blocks using HSPICE. [ABSTRACT FROM AUTHOR]

This paper presents a design methodology for robust and low-energy clock networks for ultralow voltage (ULV) circuits. We show that both clock slew and skew play important roles in achieving high maximum operating frequency (F\max) and low clock energy in ULV circuits. In addition, clock networks in ULV circuits are highly sensitive to process variations. We propose a variation-aware methodology that controls both clock skew and slew to maximize F\max and minimize clock power. In addition, we implement dynamic programming (DP)-based ULV clock routing and buffering methods (deferred merging and embedding) for deterministic and statistical conditions. Experimental results show that our clock network design method achieves lower energy (more than 20% savings) at comparable or even higher F\max compared with the existing methods. [ABSTRACT FROM AUTHOR]

This paper analyzes the effect of tier-to-tier thermal and supply crosstalk on the performance and robustness of the static random access memory (SRAM) within a 3-D stack under crosstalk influence of the logic cores. Our framework integrates distributed process variation aware circuit analysis, RC-based thermal simulation, and distributed RLC-based power delivery network simulation. The analysis shows when the logic cores and SRAMs are integrated in 3-D stack, the thermal and supply crosstalk degrade the SRAM performance and noise margin during read and write operations. [ABSTRACT FROM AUTHOR]