Search

Process-induced variability has become a predominant limiter of performance and yield of IC products especially in a deep submicron technology. However, it is difficult to accurately model systematic process variability due to the complicated and interrelated nature of physical mechanisms of variation. In this paper, a simple and practical method is presented to decompose process variability using statistics of the measurements from manufacturing inline test structures without assuming any underlying model for process variation. The decomposition method utilizes a variant of principal component analysis and is able to reveal systematic variation signatures existing on a die-to-die and wafer-to-wafer scale individually. Experimental results show that the most dominant die-to-die variation and wafer-to-wafer variation represent 31% and 25% of the total variance of a large set of manufacturing inline parameters in 65-nm SOI CMOS technology. The process variation in RF circuit performance is also analyzed and shown to contain 66% of process variation obtained with manufacturing inline parameters.

This letter reports the statistical analysis of circuit-level FET high-speed performance in 65-nm silicon-on-insulator CMOS technology. Practical performance metrics are derived from full 300-mm wafer measurements. The proposed circuit-level layout wiring parasitics-aware FET reflects realistic FET that is placed in circuits. Its measurement and model are directly applicable to circuit design in conjunction with multiple layers of yield and manufacturability considerations. A stretched gate-pitch NFET design shows an average current gain cutoff frequency fT of 250 GHz, with 7.6% standard deviation, 6.7% mismatch standard deviation, and maximum fT of 307 GHz. The proposed characterization methodology will become more relevant to technologies beyond 65 nm.

CMOS VCOs have been implemented for mm-wave applications [1–7], however, as the required channel bandwidth for these applications increases, wide-range VCO tuning is becoming more challenging. Even without taking into account the process variability in nanometer CMOS, a single VCO hardly achieves requirements for a mm-wave band and phase-noise performance, and it suffers from the steep VCO loop gain. Taking advantage of parallelism, using an array of VCOs is emerging as an alternative technique to implement a wide-band VCO (Fig. 16.3.1). While nanometer CMOS technology is becoming the next generation RF and mm-wave platform (because of high-speed performance due to technology scaling and and SoC integration capability), costly technology developments and mask sets further promote the use of array-based VCOs to expedite yield learning and circuit-development cycle. However, a VCO array requires more circuit area. Conventional designs are not scalable because of their size, cost, and complications for signal delivery. Technology scaling for mm-wave SoC is driven by the high-speed device performance while digital systems benefit from increased device density. In mm-wave applications, passive components, especially inductors, are responsible for area budget, since their area is not scaled with the technology. Taking advantage of nanometer FETs, the presented complementary LC-VCO is attractive for VCO arrays. It uses an LC-tank and its area is minimal and highly scalable. The use of state-of-the-art nanometer CMOS technology is essential to retain high-speed design margin for mm-wave circuits and provisions are required to make the complementary LC-VCO more scalable and manufacturable against the process variability and technology uncertainty. After all, the VCO array provides mm-wave-component performance-variability metrics as a feedback to the technology foundry. Such components are difficult and expensive to characterize and the required on-chip probe pads waste silicon area.

The paper presents a logic interconnect device (LID) to model digital circuit with near back-end-of-line (BEOL) effect, and to measure system performance. It is driven by a product inverter-based logic circuit, and it is loaded with near-BEOL wiring. The LID ring oscillator is measured and analyzed in 65nm SOI CMOS. The methodology offers in-situ characterization of near-BEOL interconnect parasitics, and dielectric constant in product circuits. It captures front-end-of-line (FEOL) and near- BEOL interactions, distinguished in deeply scaled CMOS.

This paper introduces a process variability model to determine the performance and yield of the cell broadband engine (CBE) in 65 nm SOI CMOS. The model incorporates spatial (die-to-die), temporal (manufacturing process drift), and parametric dimensions, and provides microprocessor performance tracking and comprehensive view on the process variability with embedded ring oscillator measurement at the wafer level. It extracts CBE performance regularity within die for the circuit design and models, and reveals the semiconductor manufacturing signatures in wafers and lots for process technology. The model reduces performance estimation testing requirements by surpassing conventional methodspsila accuracy by 28%.

A 5-stage CML prescaler operating up to 84 GHz is presented. The prescaler requirements, design considerations, simulations, and performance measurements are presented. The first divide-by-2 stage consumes 17.7mW at 1.8V, or 26.40 power-delay product per gate. The prescaler's phase noise gain degeneration at the sensitivity curve boundary is reported for the first time.

This paper presents a practical method to estimate IC product performance and parametric yield solely from a well-chosen set of existing electrical measurements intended for technology monitoring at an early stage of manufacturing. We demonstrate that the components of mmWave PLL and product-like logic performance in a 65 nm SOI CMOS technology are predicted within a 5% RMS error relative to mean.

A wideband millimeter-wave (mmWave) CML static divider fabricated in 65 nm SOI CMOS technology is presented. The mmWave system realization trend and engagement in sub-100 nm CMOS technologies are summarized. CML static dividerpsilas circuit analysis, sensitivity curve, and simulations are explored. The input-locking hysteresis and divider DC bias tuning are employed to extend the divider operation range. The divider performance measurements are presented with hysteresis-assisted gain and figure-of-merits. A scalable statistical estimation is proposed, and it is validated with a full 300 mm wafer measurements. The divider exhibits wideband mmWave performance to overcome the process variability in sub-100 nm CMOS processes.

The performance advantages in parallel ring-based VCOs are explored. When the number of VCOs is doubled, the parallel VCOs enhance phase noise by 3 dB, and the within-chip process-induced variation is reduced by 3 dB, which improves chip-limited yield. The parallel VCOs trade off circuit area and power in exchange. The parallelism advantages in analog and digital systems are compared.

The process variability of a V-band LC-VCO implemented in 65 nm SOI CMOS is examined. A complementary LC-VCO design, test set up, and measurements are presented. One lot of 300 mm wafers are measured for statistics. There are 8 wafers in the lot, and 67 VCOs per wafer. The VCO frequency tuning range statistics, analog variability against digital benchmark, yield estimation, and intra- vs. inter-wafer variations are analyzed and discussed. The VCO average frequency tuning is 63.7-69.6 GHz, and it shows 90% yield from 65.1 to 67.9 GHz.

A CML static divider operates up to 82.4 GHz with 90% yield for 0 dBm input is statistically measured and estimated. The proposed method of statistical measurement enables reliable sensitivity curve estimation by 55% of standard variation, based on the analytic model, simulations, and scalable DC and RF measurements for the first time. A 300 mm full wafer is scanned for the validation.

As an essential clock-system component, millimeter-wave dividers have been implemented for V- and W-band channels. This has also served as a standard benchmark vehicle that reveals high-speed and low-power performances of a technology. Through technology scaling, CMOS CML static divider high-frequency performances have been scaled, and they are comparable to dividers in other technologies. In addition to the device performance, circuit design and measurement determine the divider high-speed and wide frequency range performance. One of the uncertainties in CML static divider measurement is pulling and locking hysteresis. By using CML static divider topology, the divider has been assumed to have a fixed wide operation range, from DC to the fdiv , max, the maximum input-referred divider operational frequency. In fact, the CML static dividers show a certain degree of locking hysteresis, similar to injection-locking dividers. When the circuit sensitivity curve is measured, it is not clear where to set the threshold. Depending on the method, a sensitivity curve can be optimistic or pessimistic. A similar problem lies in the fdiv , max, since it changes depending on the status of a divider. Also, there have not been any analytic results that can interpret the circuit parameters and performance, in spite of the common use of sensitivity curve in literatures.

The GHz-digital clock jitter measurement capabilities in time and frequency domains are explored. A 101-stage inverter-based ring oscillator implemented in 65 nm SOI is used as a clock source. Both domains produce clock period jitters reliably. Cycle-to-cycle jitters are obtained in time, and confirmed In frequency domain. Time interval error jitters are calculated from phase noise, and time-domain results are matched with frequency-dependent jitters. The convergence and limitations of time and frequency-domain jitter measurements are presented.

This paper presents a simple yet effective method to analyze process variations using statistics on manufacturing in-line data without assuming any explicit underlying model for process variations. Our method is based on a variant of principal component analysis and is able to reveal systematic variation patterns existing on a die-to-die and wafer-to-wafer level individually. The separation of die variation from wafer variation can enhance the understanding of a nature of the process uncertainty. Our case study based on the proposed decomposition method shows that the dominating die-to-die variation and wafer-to-wafer variation represent 31% and 25% of the total variance of a large set of in-line parameters in 65nm SOI CMOS technology

A static CML divide-by-2 frequency divider is integrated in 65nm SOI CMOS. The maximum operating frequency is 90GHz while dissipating 52.4mW. The self-oscillation frequency is 92GHz with 0.57pJ switching energy. Measurement of self-oscillation frequency at multiple bias conditions enables estimation of the variation in threshold voltage, capacitance, and resistance.

This paper presents a statistical framework to cooperatively design and develop technology, product circuit, benchmarking and model early in the development stage. The statistical data- driven approach identifies device characteristics that are most correlated with a product performance, and estimates performance yield. A statistical method that isolates systematic process variations on die-to-die and wafer-to-wafer levels is also presented. The proposed framework enables translations of interactions among technology, product, and model, and facilitates collaborative efforts accordingly. The proposed methodology has been applied to first three development generations of 65 nm technology node and microprocessor product current-controlled oscillators (ICOs) for phase-locked loops (PLLs) that were migrated from 90 nm. Automated manufacturing floor in-line characterization and bench RF measurements are used for the methodology. The ICO exhibits yield improvement of RF oscillation frequency from 47% to 99% across three different 65 nm SOI technology generations.