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This article presents a direct RF-to-digital converter (RDC) for polar receivers, in which the amplitude information of the received signal is detected by a reconfigurable analog-to-digital converter (ADC) and its phase is digitized using a time-to-digital converter (TDC). The RDC prototype also includes a multi-phase reference generator and an ADC sampling position adjustment unit realizing the sub-sampling technique. Unlike conventional direct-RF sampling receivers, the proposed RDC samples the input RF signal at the baseband rate. The RDC is capable of digitizing a variety of modulation waveforms, such as quadrature amplitude modulation (QAM), phase shift keying (PSK), and amplitude phase shift keying (APSK). When comparing QAM to APSK, the later has advantages of relaxed system requirements on phase noise and linearity. The proposed direct RF-to-digital polar converter IC achieves a maximum data rate of 1.94 GB/s with a 1024-APSK modulation at a carrier frequency of 6 GHz, while consumes only 3.8 mW power under 1.1 V supply.

Integrated circuits, especially analog circuits, are highly sensitive to process, voltage, and temperature (PVT) variations. The information processed by analog circuits is often embedded in the amplitude of the waveforms, which requires circuits with high precision and high linearity. On the other hand, analog signal processing in time domain, such as (TDCs) and digital to-time converters (DTCs), was not widely adopted until the late 1990s when semiconductor technology advanced to the sub-micrometer region.

A fractional-N digital phase-locked loop (PLL) architecture with low fractional spur is presented in this paper. A 2-D Vernier time-to-digital convertor (TDC) is implemented to achieve wide detection range with fine resolution. The TDC is calibrated automatically utilizing the ramp signal generated from the fractional-N accumulator for optimal linearity. A digi-phase spur cancellation technique with automatic TDC gain tracking is also implemented to further suppress the fractional spurs. The chip also includes an improved multimodulus divider (MMD) structure that overcomes the glitch problem during division ratio toggling associated with the prior art MMDs, enabling carrier synthesis across wide frequency range continuously. As part of an 802.11a/b/g/n transceiver, the DPLL can provide coverage for both 2.4/5 G WiFi bands. The proposed fractional-N DPLL is implemented in a 55-nm CMOS technology. The DPLL achieves a largest fractional spur level of −55 dBc without using a sigma–delta modulator and an in-band phase noise of −107 dBc/Hz (0.55 ps integrated jitter) while consuming 9.9 mW.

This paper presents a direct RF-to-digital converter (RDC) for polar RX. It consists of a pair of TDCs, an ADC, and a precise sampling position control system. Unlike conventional direct-RF sampling receivers, the RDC samples the input RF signal at baseband rate. It is capable of directly digitizing the phase and amplitude of the received modulated RF signals. It is compatible with a variety of modulations and has advantages of relaxed system requirements on phase noise and linearity when APSK is used. The RDC achieves a max rate of 1.94 GB/s with 1024-APSK at a carrier of 6 GHz, consuming only 3.8mW.

This paper presents the design of a fully self-timed 8-bit 80-Ms/s single-core SAR ADC with interleaved comparators and a high order compensated opamp-less bandgap reference. A 3/2 interleaving algorithm was designed for better SFDR performance, where two of the three comparators are orderly chosen for interleaving in each conversion while offset calibration is applied to the idle comparator. Asynchronized SAR logic with a DAC settling timer is designed for fully self-timing of the ADC. The ADC was designed with a PVT stabilized on-chip reference source which promises a stable reference for the ADC at extreme temperature environments such as aerospace exploration or quantum computing. Technique for compensating the temperature coefficient (TC) of a bandgap reference (BGR) using temperature characteristics of transistor's current gain β is proposed. Measured results show 42.8dB SNDR, 56.8 dB SFDR and −53.3dBc THD for the proposed SAR ADC, drawing 1.07mW from a 1.1v supply. Measured average TC of the HBT proposed BGR is 23ppm/°C and 39 ppm/°C over the commercial (0∼70°C) and space (−260∼125°C) temperature ranges, respectively. The BGR reaches PSRR of −50dB at 1MHz, and −38dB at 1GHz. The entire chip was implemented on 0.13um 8HP SiGe process with an active area of 0.2952 mm2.

This paper presents a successive approximation register (SAR) assisted hybrid analog to digital converter (ADC) that uses a time domain quantizer for sub-range quantization. The proposed hybrid ADC utilizes an 8b 2bit-per-cycle SAR coarse ADC pipelined with a 6b 2-dimensional Vernier time-to-digital converter (TDC) as the fine quantizer for high-resolution and high conversion rate. Different from the conventional approach, the voltage residue is converted into time domain for fine quantization which greatly relaxes the power-to-noise requirement of the comparator for high-resolution. Moreover, the 8b coarse quantization stage greatly reduces the range of the residue signal and thus dramatically relieves the linearity requirement of the voltage-to-time (V-T) conversion. The LSB of the TDC is digitally calibrated thus the gain accuracy of the pipeline stage is relaxed. The prototype was fabricated in a 45nm CMOS process, and the ADC core dissipates 3.66 mA from a 1-V supply with an active area of 0.08 mm2. The prototype chip achieves a measured peak SNDR of 65.7dB and SFDR of 80.7dB at conversion rate up to 280MS/s. The calculated Walden and Schreier figures-of-merit (FoM) are 8.4fJ/conv.-step and 171.5dB, respectively.

This paper presents a time-to-digital (TDC) design with large detectable range and fine resolution, combining a ring TDC with a 2-dimentional (2D) Vernier TDC. The detectable range has been greatly increased to 14 bits with the ring structure. A 1-ps resolution was achieving with 2D Vernier architecture. Utilizing the 2nd order ΔΣ modulators (SDM) and a 2D spiral arbiter array, the proposed TDC greatly mitigates the quantization errors introduced by digitally controlled delay cells and the intrinsic arbiter line folding errors associated with the 2D array topology. The measured maximum DNL/INL are 0.41/0.79ps with ΔΣ linearization. A prototype TDC chip fabricated in 130nm CMOS technology achieves a conversion rate of 10 MS/s while consumes 2.4 mW power.

This work presents an 8-bit 1.25ps resolution Vernier TDC with 2D reconfigurable spiral arbiter array and ΔΣ linearization for ADPLL. The 2D spiral arbiter array improves both linearity and detection range. The quantization errors introduced by delay cells and 2D arbiter array folding points are minimized using a reconfigurable arbiter array with 2nd order ΔΣ modulators. The prototype in a 45nm CMOS technology consumes 0.3mW power under a 1V power supply with 80MHz conversion rate. The measured maximum DNL/INL are 0.31/0.4 ps with ΔΣ linearization and 1.35/1.03 ps without ΔΣ linearization, respectively.

This work presents a 1.9∼5.6 GHz fractional-N DPLL with digi-phase spur canceller. It utilizes a ramp signal generated from the fractional-N accumulator to automatically calibrate the TDC linearity. The chip also includes an MMD that overcomes the division ration skipping problem associated with the prior art MMDs. The ADPLL achieves a worst fractional spur level of −55 dBc and an in-band phase noise of −109 dBc/Hz (0.63 ps integrated jitter) while consuming 9.9 mW.