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The envelope tracking (ET) design methodology is routinely adopted to improve the efficiency of radio frequency power amplifiers (PAs). One shortcoming of state-of-the-art ET PAs is that their supply modulators are usually designed and optimized for a single communications standard. They are either incompatible in modern communication devices where multiple communications standards are used, and/or the efficiency unoptimized when the devices operate in standards other than the designed standard. To circumvent this shortcoming, a novel supply modulator for multistandard communications is proposed. The proposed design embodies a proposed dual-mode Sigma–Delta control block and an adaptive biasing Class AB amplifier, which allows the supply modulator self-adjusting its operation and optimizing the efficiency according to the application. A prototype supply modulator IC is designed and fabricated using a 180 nm CMOS process. Based on measurements, the proposed supply modulator features the highest static efficiency of 91% and the highest 3 dB backoff static and dynamic efficiency compared to the state-of-the-art supply modulators. When tracking 40 MHz LTE-A envelope signals, the prototype supply modulator achieves a high efficiency of 85% at 1.8 W output power, and the efficiency remains high >80% for a wide range of output power, from 0.5 to 1.8 W.

Design and Analysis of Audio Class D Amplifiers Abstract Class-D Amplifiers (CDAs) are at this juncture widely accepted over their linear counterparts due to their higher power-efficiency and their ensuing smaller form factor, and the design art thereto is relatively mature. Nevertheless, despite their maturity, the electronics industry desires CDAs with substantially improved specifications, including higher linearity (often qualified by Total Harmonic Distortion + Noise (THD+N) and Intermodulation Distortion (IMD)) and higher immunity to supply noise (often qualified by Power Supply Rejection Ratio (PSRR) and Power Supply induced Intermodulation (PS-IMD)). The broad objective of this Ph.D. program is to design CDAs with said improved specifications – on the basis of analytical investigations (into the mechanisms of and the circuit parameters affecting the various specifications of CDAs) and design and monolithic realization of CDA prototypes (embodying novel architectures and/or circuits). The specific CDA architectures of interest are the somewhat esoteric ultra-low-power Bang-bang Control CDAs (appropriate for power-critical wearable devices) and the ubiquitous Pulse-Width-Modulation (PWM) CDAs (appropriate for general audio applications). A number of contributions are made herein. First, to improve the linearity of Bang-bang control CDAs, their IMD is analytically investigated to ascertain the mechanisms thereto and to derive expressions to analytically model the IMD; it is interesting that despite its imperativeness, the IMD of Bang-bang CDAs remains unreported/uninvestigated in literature. From our analysis, we observe the interesting phenomenon of the presence of even-order IMD that is usually negligible/unreported in CDAs (and in linear amplifiers); as expected, odd-order IMD is also present. We show that in some practical scenarios, the even-order IMD can be unexpectedly dominant over the odd-order IMD. The derived analytical expressions for the IMD are verified by simulations and on the basis of measurements on a physical CDA. This analysis is insightful and useful as it provides an analytical basis to model the IMD of Bang-bang CDAs, hence their linearity, and delineates the possible trade-offs in relation to other imperative parameters (e.g. PSRR) to mitigate the IMD. Second, to improve both the linearity and the supply noise immunity of PWM CDAs, a novel PWM CDA design is proposed and a fully-integrated prototype CDA (65nm CMOS) realized. The proposed design, embodying a novel carrier generator and the first-ever ‘phase-error-free’ PWM modulator, circumvents the otherwise undesirable trade-offs in conventional designs that involve linearity and noise immunity (and power-efficiency and Electromagnetic Interference, EMI). On the basis of measurements on the prototype CDAs, the proposed design achieves not only the highest PSRR reported to-date, but also the highest Figures-of-Merit (FOMs) when benchmarked against reported state-of-the-art CDAs. Third, we identify that the ground-bounce in CDAs can drastically degrade the linearity (and reliability) of CDAs (all CDAs including the Bang-bang and PWM CDAs). Interestingly, this phenomenon has not been analytically investigated/reported in literature, and the means for its mitigation are largely empirical. We complete the first-ever analytical investigation to ascertain the mechanisms of and the circuit parameters affecting the ground bounce, and its effects on CDAs. We show that the generally-accepted and/or intuitive ‘knowhow’ for mitigating ground bounce may unexpectedly exacerbate ground bounce – the effect is instead the converse and adverse. On the basis of this investigation, we propose a complete design methodology to reduce the ground-bounce and its effects on CDAs, and further propose a ground-bounce-aware dead-time circuit design to mitigate the ground bounce effects. The efficacy of the proposed design methodology and proposed dead-time circuit are verified by means of measurements and simulations. Specifically, a PWM CDA optimized with said methodology and embodying said dead-time circuit features significantly higher linearity (4 times lower THD) compared to the same CDA without said optimization and embodiment. DOCTOR OF PHILOSOPHY (EEE)

Although class D amplifiers (CDAs) are highly advantageous over their linear amplifier counterparts in terms of power efficiency, their power efficiency remains undesirably low at nominal operation conditions where the output power is $\sim$ 26 dB lower than its peak output power (due to the large crest factor of the audio/speech signal and headroom for adjustment). This is particularly the case for power-critical micropower applications such as hearing instruments. At nominal conditions, we find that the overcurrent protection circuit (for the output stage) is unexpectedly the most power-dissipative block in micropower CDAs. In this brief, we propose a novel ultralow-power overcurrent protection circuit, which features 67% lower power dissipation compared to conventional overcurrent protection circuit without compromising the IC area. To further verify the advantages of the proposed overcurrent protection circuit, an ultralow-power bang–bang CDA is designed. We show that, by employing the proposed overcurrent protection circuit, the power efficiency of the bang–bang CDA is significantly improved from 10.5% to 23.7% for a 64- $\Omega$ load and from 1.8% to 4.7% for a 400- $\Omega$ load.

Audio Class D amplifiers (CDAs) based on bang-bang architecture are arguably the most power efficient architecture of all CDAs reported to-date due to their sheer hardware simplicity. At this juncture, the intermodulation distortion (IMD), an imperative measure that defines fidelity, remains unreported for bang-bang CDAs. In this paper, we investigate the mechanisms of and circuit parameters affecting the IMD of bang-bang CDAs. An interesting phenomenon is that the even-order IMD which is usually negligible/unreported in other CDAs and linear amplifiers may be higher than odd-order IMD therein. We derive analytical expressions for the IMD of the ideal and practical bang-bang CDAs, and the derived expressions are verified against HSPICE simulations and on the basis of measurements on a physical bang-bang CDA. These derived analytical expressions are useful as they provide valuable insights to the design of bang-bang CDAs and how parameters can be tradedoff to improve the IMD.

Present-day smartphones and tablets demand high audio fidelity (e.g., total harmonic distortion + noise, THD + N ≪ 0.01%), and high noise immunity (e.g., power supply rejection ratio, PSRR ≫ 80 dB) to allow high integration in an SoC. The design of conventional closed-loop pulse width modulation (PWM) Class-D amplifiers (CDAs) typically involves undesirable trade-offs between fidelity (qualified by THD + N), PSRR and switching frequency. In this paper, we propose a fully integrated CMOS CDA that embodies a novel input-modulated carrier generator and a novel phase-error-free PWM modulator, collectively allowing the employment of high loop-gain to achieve high PSRR, yet without compromising linearity/dynamic-range or resorting to high switching frequency. The prototype CDA, realized in 65 nm CMOS, achieves a THD + N of 0.0027% and a power efficiency of 94% when delivering 500 mW to an 8 Ω load from V DD = 3.6 V. The PSRR of the prototype CDA is very high, -101 dB @217 Hz and 90 dB @1 kHz, arguably the highest to-date. Furthermore, the switching frequency of the prototype CDA varies from ~320 to 420 kHz, potentially reducing the EMI due to spread-spectrum. In addition, the prototype CDA is versatile with a large operating-voltage range, with V ranging from rechargeable 1.2 V single battery to standard 3.6 V smart-device supply voltages.

Of the reported modulation techniques for Class D amplifiers (CDAs), CDAs based on Bang-Bang control modulation are arguably the most advantageous in terms of power-efficiency for low-power power-critical applications. To date, only single-ended and 2-state Bang-Bang control CDAs have been reported, and are hence disadvantageous because they require a bulky and costly output lowpass filter. In this paper, we propose the first-ever 3-state Bang-Bang control filterless CDA applicable to regular-power and ultra-low-power applications. Compared to other filterless 3-state CDAs, the proposed filterless 3-state Bang-Bang control CDA features the simplest hardware and the highest power-efficiency, but with somewhat compromised fidelity. Nevertheless, the fidelity thereto is sufficient for typical ultra-low-power applications such as low-to-mid performance wearable devices.

Class D amplifiers are routinely employed in power-critical hearing aids for their high power-efficiencies, typically ~90% at high modulation indexes. Nevertheless, at the nominal operation condition where the modulation index M=0.1, the power-efficiency is typically 32%. In this paper, we show that the comparator embodied in the over-current protection circuit of the Class D output stage is dominant at M=0.1. We propose the design of a novel comparator (with performance parameters comparable with conventional comparators) featuring ~40% lower power dissipation. This improved lower power dissipation translates to a worthwhile 12% improvement in the power-efficiency of the Class D amplifier output stage. The proposed design herein is verified by computer simulations.

Open-Loop Pulse Width Modulation (PWM) Class D amplifiers are attractive for power critical applications including hearing aids due to their simple hardware and high power-efficiency. Nevertheless, a drawback of open-loop Class D amplifiers is their susceptibility to supply noise, quantified by power supply rejection ratio (PSRR) and power supply induced intermodulation distortion (PS-IMD). In this paper, PSRR and PS-IMD of a commonly-used carrier generation method are investigated and compared against other common carrier generation methods. The analyses are verified by means of HSPICE simulations. The analyses and comparisons provide designers useful insight to the design of power critical Class D amplifiers.