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Across-wafer gate critical dimension (CD) uniformity impacts chip-to-chip performance variation vis-a-vis speed and power. Performance specification for across-wafer CD uniformity has become increasingly stringent as linewidth decreases to 90 nm and below. This paper presents a novel approach to improve across-wafer gate CD uniformity through the lithography and etch process sequence. The proposed approach is to compensate for upstream and downstream systematic CD variation components in the litho-etch process sequence by optimizing across-wafer post exposure bake (PEB) temperature profiles. More precisely, we first construct a temperature-to-offset model that relates the PEB temperature profiles to the setpoint offsets of multi-zone PEB plates. A second model relating across-wafer CD to setpoint offsets of PEB plates is then identified from CD scanning electron microscope measurements. Post-develop and post-etch CD uniformity enhancement methodologies are then proposed based on the CD-to-offset model and temperature-to-offset models. The temperature-to-offset model is determined to be more appropriate for use in CD uniformity control due to its superior fidelity and portability as compared with the CD-to-offset model. We demonstrate that about 1-nm reduction in standard deviation of post-etch CD variation was achieved in the verification experiment, which validated the efficacy of proposed CD uniformity control approach.

As the semiconductor industry enters the 45nm node and beyond, the tolerable lithography process window significantly shrinks due to the decreasing k 1 factor and increasing lens NA required to meet product shrink goals. The usable depth of focus at the 45nm node for critical layer is less than 200nm and for the 32nm node it will approach 100nm. Consequently, process window aware Optical Proximity Correction (OPC) and Lithography Rule Check (LRC) become crucial to ensure the robustness of OPC to focus and dose variation. An accurately calibrated continuous process window model is the corner stone for successful process variation aware OPC and LRC. For ease of use, this calibrated model should be a continuous function of defocus and dose and able to interpolate and extrapolate in the usable process window. Lithographic proximity effects have an optical component and a resist component. As state of the art OPC simulation tool is capable of precise and fast optical simulation, however its treatment of chemical amplified resist effects is relatively crude and does not capture the complex behavior during acid & quencher reaction, diffusion and development. This in turn causes difficulties for a continuous process window model where the resist component plays an important role. We proposed a hybrid resist model, which is a superposition of a traditional OPC chemical amplified resist model and a first order resist bias model. Using Synopsys' OPC modeling software package-ProGen, we incorporated this hybrid resist model into the continuous process window (PW) modeling module, and very good model calibration performance was achieved.

Production optical proximity correction (OPC) tools employ compact optical models in order to accurately predict complicated optical lithography systems with good theoretical accuracy. Theoretical accuracy is not the same as usable prediction accuracy in a real lithographic imaging system. Real lithographic systems have deviations from ideal behavior in the process, illumination, projection and mechanical systems as well as in metrology. The deviations from the ideal are small but non-negligible. For this study we use realistic process variations and scanner values to perform a detailed study of useful OPC model accuracy vs. the variation from ideal behavior and vs. theoretical OPC accuracy. The study is performed for different 32nm lithographic processes. The results clearly show that incorporating realistic process, metrology and imaging tool signatures is significantly more important to predictive accuracy than small improvements in theoretical accuracy.

The requirement for OPC modeling accuracy becomes increasingly stringent as the semiconductor industry enters sub- 0.1um regime. Targeting at capturing the IC pattern printing characteristics through the lithography process, an OPC model is usually in the form of the first principle optical imaging component, refined by some phenomenological components such as resist and etch. The phenomenological components can be adjusted appropriately in order to fit the OPC model to the silicon measurement data. The optical imaging component is the backbone for the OPC model, and it is the key to a stable and physics-centric OPC model. Scanner systematic signatures such as illuminator pupil-fill, illuminator polarization, lens aberration, lens apodization, flare, etc., previously ignored without significant accuracy sacrifice at previous technology nodes, but are playing non-negligible roles at 45nm node and beyond. In order to ensure that the OPC modeling tool can accurately model these important scanner systematic signatures, the core engine (i.e. the optical imaging simulator) of OPC simulator must be able to model these signatures with sufficient accuracy. In this paper, we study the impact on optical proximity effect (OPE) of the aforementioned scanner systematic signatures on several 1D (simple line space, doublet line and doublet space) and 2D (dense line end pullback, isolated line end pullback and T-bar line end pullback) OPC test patterns. We demonstrate that the scanner systematic signatures have significant OPE impact on the level of several nanometers. The predicted OPEs and impact from our OPC simulator matches well with results from an industry standard lithography simulator, and this has laid the foundation of accurate and physics-centric OPC model with the systematic scanner signatures incorporated.

An accurate process model has always been the key for successful implementation of model-based Optical Proximity Correction (OPC). As CD control requirements become severe at the 45nm and 32nm device generations, process model accuracy requirements become more stringent. In previous generations, certain systematic process and tool fingerprints could be safely ignored. For example, lens apodization and mask pellicle film induced transmission loss, lens vectorial fingerprint(i.e. Jones pupil), illuminator polarization profile, and etc were ignored in conventional OPC modeling approaches. These effects are now playing a more important role in OPC modeling as technology scales down. Using conventional OPC model may lead to under-correction of the design layout during OPC, and this will result in large number of post-OPC layout hot spots which have patterning issues when the OPCed layout is exposed on the scanner. We designed an OPC correction and verification flow which can efficiently capture the post-OPC layout hot spots due to under-correction using traditional OPC model, and this flow further fixes these detected hot spots. Our simulations demonstrated that this proposed flow is able to achieve an OPC performance of 2.25nm CD error range and 0.26nm CD error standard deviation on poly gate layer for 45nm SRAM design. And this validated the efficiency of the proposed flow.

Low pass filtering taking place in the projection tools used by IC industry leads to a range of optical proximity effects resulting in undesired IC characteristics. To correct these predicable OPEs, EDA industry developed various, model-based correction methodologies. Of course, the success of this mission is strongly dependent on how complete the imaging models are. To represent the image formation and to capture the OPEs, the EDA community adopted various models based on simplified representations of the projection tools. Resulting optical proximity correction models are capable of correcting OPEs driven by the fundamental imaging conditions such as wavelength, illuminator layout, reticle technology, and lens numerical aperture, to name a few. It is well known in the photolithography community that OPEs are dependent on the scanner characteristics. Therefore, to reach the level of accuracy required by the leading edge IC designs, photolithography simulation has to include systematic scanner fingerprint data. These tool fingerprints capture excursions of the imaging tools from the ideal imaging setup conditions. They quantify the performance of key projection tool components such as illuminator and lens signatures. To address the imaging accuracy requirements, the scanner engineering and the EDA communities developed OPC models capable of correcting for imaging tools engineering attributes captured by the imaging tools fingerprints. Deployment of immersion imaging systems has presented the photolithography community with new opportunities and challenges. These advanced scanners, designed to image in deep sub-wavelength regime, incorporate features invoking the optical phenomena previously unexplored in commercial scanners. Most notably, the state of the art scanners incorporate illuminators with high degree of polarization control and projection lenses with hyper-NAs. The image formation in these advanced projectors exploits a wide range of vectorial interactions originating at the illuminator, on the pattern mask, in the projection lens and at the wafer. The presence of these, previously subdued phenomena requires that the imaging simulation methodologies be refined, increasing the complexity of the OPE models and optical proximity correction methodologies.

As scanner projection lens captures only a finite number of IC pattern diffraction orders. This low pass filtering leads to a range of optical proximity effects such as pitch-dependent CD variations, corner rounding and line-end pullback, resulting in imaged IC pattern excursions from the intended designs. These predictable OPEs are driven by the imaging conditions, such as wavelength, illuminator layout, reticle technology, and lens numerical aperture. To mitigate the pattern excursion due to OPEs, the photolithography community developed optical proximity correction methodologies, adopted and refined by the EDA industry. In the current implementations, OPC applied to IC designs can correct layouts to compensate for OPEs and to provide imaged patterns meeting the design requirements.

It has been shown that across-wafer CD (critical dimension) uniformity can be improved by compensating for systematic CD variations through the litho-etch sequence by tuning the across-wafer PEB temperature profile1. Earlier work describes the approach to enhance post-develop CD uniformity (CDU) utilizing temperature-to-offset model in conjunction with resist CD's PEB sensitivity. Taking into consideration CD variation induced by plasma etch, we then develop a methodology to improve the post-etch poly CDU. This is done using constrained quadratic optimization techniques. Considering the fact that isolated, semi-isolated and dense lines in multiple sizes coexist on an actual chip, it is desirable to have simultaneous CDU control for isolated, semi-islolated and dense lines of various sizes. In this paper we expand our CDU control concept to simultaneous CDU control for multiple CD targets and propose the use of multi-objective and minimax optimization schemes. A combination of experimental and simulated runs is used to test this approach.

This paper describes a novel approach to improving across-wafer CD uniformity through the litho-etch sequence. Our approach is to compensate for systematic CD perturbations by employing all available control authority though the litho-etch process sequence. In particular, we find that the most effective control input for regulating spatial variations in CD is found in the post exposure bake (PEB) process step. More precisely, we construct offset models that relate the PEB temperature profiles of multi-zone bake plates to their zone offsets using wireless, in-situ temperature sensors from OnWafer Technologies. A second model relating across-wafer CD to PEB bake plate zone offsets is then identified from CD data measured by CD-SEM. The CD-to-offset model and the temperature-to-offset model are used with knowledge of the resist sensitivity to determine optimal bake plate zone offsets which minimize post-etch CD variation. This is done using constrained quadratic optimization techniques. Partial experimental work and simulation results show the promise of our approach. We demonstrate through simulation that across-wafer CD variation can be significantly reduced for 150nm technology node and beyond.

An accurate optical model is the foundation of an accurate optical proximity correction (OPC) model, which has always been the key for successful implementation of model-based OPC. As critical dimension (CD) control requirements become severe at the 45- and 32-nm device generations, OPC model accuracy and hence optical model accuracy requirements become more stringent. In previous generations, certain optical effects could be safely ignored. For example, the transmission attenuation particularly at high spatial frequencies caused by lens apodization effects and organic pellicle films was ignored or not accurately modeled in conventional OPC simulators. These effects are now playing a more important role in OPC modeling as technology scales down. Our simulations indicate these effects can cause CD modeling errors of 5 nm or larger, at the 45-nm technology node and beyond. Therefore, they must be accurately modeled in OPC modeling. In our OPC modeling methodology, we propose two novel low-pass-filter models to capture the frequency-dependent transmission attenuation due to lens apodization and to pellicle films. These parameterized novel low-pass-filter models ensure that lens apodization and pellicle-film-induced transmission attenuation can be appropriately account for through regression during the experimental OPC model calibration stage in the case where no measured transmission data are available, thus enabling physics-centric OPC model building with considerably higher accuracy. We can then avoid overfitting the OPC model, which could cause instability in the OPC correction stage. The validity and efficiency of the proposed novel models are also verified using an industry-standard lithography simulator as well as an experimental OPC model calibration at the 45-nm technology node.