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Water being used for any purpose needs to adhere to a certain quality standard. Performing tests to ensure water quality can be done in an analytical laboratory with high precision using a wide range of techniques and equipment. There is a growing need, however, for low-cost point-of-need (PON) solutions that would be able to serve a larger portion of earth’s population. One of the techniques, Impedance Spectroscopy (IS), measures the impedance of a water sample across a wide range of frequencies in order to analyse some frequency dependent properties of a sample. The problem addressed in this project is to develop an inexpensive, PON, system that can perform Impedance Spectroscopy on water samples. The impedance spectroscopy system is being developed in CMOS using the 0.35um ams AG process and will produce an impedance spectrum with frequencies ranging from 1 Hz to 10 MHz. The system interfaces with water samples through a standard three-point electrode, with voltage signals being maintained between the reference and working electrode. The analog front end for measurement as well as the digital control circuitry is included in the CMOS design.

This paper covers the design of a complementary metal oxide semiconductor (CMOS) pixel readout circuit with a built-in frequency conversion feature. The pixel contains a CMOS photo sensor along with all signal-to-frequency conversion circuitry. An 8×8 array of these pixels is also designed. Current imaging arrays often use analog-to-digital conversion (ADC) and digital signal processing (DSP) techniques that are off-chip1. The frequency modulation technique investigated in this paper is preferred over other ADC techniques due to its smaller size, and the possibility of a higher dynamic range. Careful considerations are made regarding the size of the components of the pixel, as various characteristics of CMOS devices are limited by decreasing the scale of the components2. The methodology used was the CMOS design cycle for integrated circuit design. All components of the pixel were designed from first principles to meet necessary requirements of a small pixel size (30×30 μm2) and an output resolution greater than that of an 8-bit ADC. For the photodetector, an n+-p+/p-substrate diode was designed with a parasitic capacitance of 3 fF. The analog front-end stage was designed around a Schmitt trigger circuit. The photo current is integrated on an integration capacitor of 200 fF, which is reset when the Schmitt trigger output voltage exceeds a preset threshold. The circuit schematic and layout were designed using Cadence Virtuoso and the process used was the AMS CMOS 350 nm process using a power supply of 5V. The simulation results were confirmed to comply with specifications, and the layout passed all verification checks. The dynamic range achieved is 58.828 dB per pixel, with the output frequencies ranging from 12.341kHz to 10.783 MHz. It is also confirmed that the output frequency has a linear relationship to the photocurrent generated by the photodiode.

The work presented details the development of a low-cost potentiostat, with the aim of creating an ink-jet printed hybrid paper-based low-cost sensing system for rapid water quality monitoring. Potentiostats exhibit high sensitivities and can be used for a variety of applications. In this application, they use electrochemical techniques to detect heavy metals via stripping analysis. The potentiostat front-end, consisting of an LMP91000 sensing chip, was designed and manufactured on a printed circuit board (PCB) and compared to a laboratory-based potentiostat using cyclic voltammetry performed using an 80 sl sample of 5 mM ferri-ferrocyanide dropped onto a commercial screen-printed electrode. The results obtained from the PCB potentiostat are comparable to those obtained using the development board and the laboratory-based potentiostat. The results highlight the functionality of a low-cost point-of-need potentiostat that can be used for environmental monitoring as well as the feasibility of transferring the design to a paper substrate.

This paper presents the design of a low-complexity, linear and sub-pF CMOS capacitance-frequency converter for reading out a capacitive bacterial bio/sensors with the endeavour of creating a universal bio/sensor readout module. Therefore the priority design objectives are a high resolution as well as an extensive dynamic range. The circuit is based on a method which outputs a digital frequency signal directly from a differential capacitance by the accumulation of charges produced by repetitive charge integration and charge preservation1. A prototype has been designed for manufacture in the 0.35 μm, 3.3V ams CMOS technology. At a 1MHz clock speed, the most pertinent results obtained for the designed converter are: (i) power consumption of 1.37mW; (ii) a resolution of at least 5 fF for sensitive capacitive transduction; and (iii) an input dynamic range of at least 43.5 dB from a measurable capacitance value range of 5 – 750 fF (iv) and a Pearson’s coefficient of linearity of 0.99.

Three basic translinear circuit topologies are modified for use at low supply voltage. They are: (1) the balanced translinear loop; (2) the alternating translinear loop; and (3) the instantaneous-companding integrator. The key to this work is the constructive use of nonsaturated MOS transistors operating in weak inversion. This provides two improvements. First, circuit operation is extended to low supply voltage. Second, accurate realization is enabled since the circuits become immune to MOS body-effect. The proposed techniques are suitable for static and dynamic analog signal processing circuits in mixed-signal chips fabricated in digital CMOS technology and operating at the minimum possible supply voltage.

A gain-enhancement technique based on active bootstrapping is proposed which ideally increases the low-frequency gain by two gain stages with no speed penalty and without adding to the phase shift. Therefore, high-frequency performance and feedback stability are not compromised. In practice, the gain enhancement will be limited by nonidealities. The technique is particularly suited for minimum supply voltages since no cascodes are used and, although the discussion pertains to CMOS, can also be applied in bipolar and BiCMOS technologies. A complete analysis, including the effects of nonidealities, is performed. A generally applicable design methodology is formulated.

In CMOS, an SRAM cell containing six transistors is generally used. If a smaller number of transistors and fewer connection lines were possible, the packing density of SRAM chips may be improved. A reduce-area four-transistor SRAM cell for implementation in a standard digital CMOS process is proposed in this paper.

This paper proposes a programmable integrated circuit (IC) prototyping system. Most IC designs can be implemented by simply programming the device with an appropriate switching map. The device can later be reprogrammed with a modified, or completely different circuit. This allows cheap, rapid prototyping of ICs for the purpose of teaching IC design.

Multiple input floating gate (MIFG) transistors have been found to be very useful in many analogue applications. We extend the existing MIFG models to cover switched operation and charge injection, extending the usefulness of MIFGs to many new applications.

In CMOS, an SRAM cell containing six transistors and five routing wires is generally used. If a smaller number of transistors and/or fewer connection lines were possible, the packing density of SRAM chips may be improved. In this paper, a four-transistor SRAM cell for implementation in a standard digital CMOS process is proposed. The implementation of the smallest area cell in a 1.2 /spl mu/m n-well CMOS process shows successful cell operation. Two memory block architectures are also discussed, as well as the specific cell configurations for correct operation. Depending on the memory block architecture, the four-transistor cell area reduction, when compared to a six-transistor cell, is either 14.7% or 37.3%.

A small area, wide dynamic range, four quadrant analogue CMOS multiplier is presented, based on capacitively coupled dual-gate (CCDG) MOSFETs. Models are developed, and the multiplier is simulated with these models. The properties and advantages of the CCDG MOSFET in multipliers are shown, also by comparison with an existing multiplier.

A simple CMOS circuit is reported for generating supply-independent bias voltages and currents, down to a minimum supply voltage. The circuit is compatible with digital processes. Supply interference is rejected by >40 dB for all frequencies.