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An extended model of through-silicon via (TSV)-based solenoid inductor is proposed to save on-chip areas for 3-D radio frequency (RF) ICs and package integration. To achieve a high inductance density, the nested topology consists of high-density TSVs in high-resistivity silicon substrate and multilayers of metals in compatible CMOS process. Then, an analytical inductance model, considering the mutual inductance of TSVs and complicated metal traces, is established and verified. The inductance variation in physical dimensions is studied based on the modeled and simulated results of a TSV solenoid inductor in single tier. The proposed TSV solenoid typology gets better performance at inductance density and quality factor around some frequencies through analytical model and full-wave simulations. Further studies are directed toward RF application overview according to broadband and low power consumption.

In this paper, we change terminal loads of a microstrip line to separate electric field coupling and magnetic field coupling between a microstrip line and a transverse electromagnetic (TEM) cell during radiated emission measurement. Such separation can also be validated by another terminal load. After validation, the effect of termination on both couplings is investigated, and the requirements of termination impedance to suppress the two couplings are revealed. In addition, we find that the linear physical models deriving both lumped coupling parameters only hold below a limited frequency.

In this paper, we investigated on -state electroluminescence (EL) characteristics in fresh GaN-based HEMTs under different on -state bias conditions. It demonstrated that: 1) the intensity of the on -state EL emitted by the GaN-based HEMTs with relatively high ${\rm V}_{\rm DS}$ $({\rm V}_{\rm DS}>10\ \hbox{V} )$ monotonically increased as the gate voltage increased; and 2) the distribution of the intensity of the on -state EL was uniform along the gate and across the device before stress tests. The degradation process and mechanisms of the devices in the high temperature operation (HTO) stress were also analyzed based on the on -state EL characterization, the electrical measurement, and failure analysis. It demonstrated the following. First, the on -state EL distribution of the device after step HTO (S-HTO) stress tests was no longer uniform along one of the fingers, which indicated that the degradation was related to this finger. This hypothesis was confirmed by the SEM observation after the deprocess of the gate metal and the SiN passivation layer. Second, a new degradation mechanism of AlGaN/GaN HEMTs that caused the abrupt degradation in the S-HTO stress was identified and related to the emergent, localized, and jagged crack under the gate metal. Third, there was no abrupt degradation in the long-term HTO (LT-HTO) stress test. However, the on -state EL intensity of the inner fingers in the device after the LT-HTO stress test decreased more than that of the outer fingers, which meant that the degradation of the inner fingers was faster than that of the outer fingers as a result of the higher temperature caused by self-heating in the inner region of the device. Finally, the gradual degradation in the LT-HTO stress test was ascribed to the gradual formation of structural damage along the drain side of the whole gate edge, which was confirmed by the SEM observation.

Single event effects (SEE) in two commercial-off-the-shelf (COTS) Ferroelectric Random Access Memory (FeRAM) technologies were investigated by heavy ions and pulsed laser irradiation. At least six SEE types were observed. The majority of the errors were caused by anomalies in the peripheral circuit, which was confirmed by the mirror SRAM technique, non-volatile test mode, and the detailed error information. Single event upset, single event functional interrupt and single event latchup cross sections were reported, with weak dependence on the supply voltage.

Hardware Trojan embedded by adversaries has emerged as a serious security threat. Until now, there is no a universal method for effective and accurate detection. Since traditional analysis approaches sometime seem helpless when the Trojan area is extremely tiny, this paper will focus on the novel detection method based on frequency spectrum analysis. Meanwhile, a failure physics model is presented and depicted in detail. A digital CORDIC IP core is adopted as a golden circuit, while a counter is utilized as a Trojan circuit. The automatic test platform is set up with Xilinx FPGA, LabVIEW software, and high precision oscilloscope. The power trace of the core power supply in FPGA is monitored and saved for frequency spectrum analysis. Experimental results in time domain and frequency domain both accord with those of theoretical analysis, which verifies that the proposed failure physics model is accurate. In addition, due to immunity to vast measurement noise, the novel method processing in frequency domain is superior to the traditional method conducting in time domain. It can easily achieve about 0.1% Trojan detection sensitivity, which indicates that the novel detection method is effective.

This paper proposed a two-dimensional thermal impedance model for amorphous silicon thin film transistors (a-Si:H TFTs) from a system of coupled energy equations, heat flowing equations and boundary conditions. By using of this model, the channel temperature distribution and thus the maximum channel temperature can be calculated. This model can be applied to describe the thermal behavior and thermal reliability of a-Si:H TFTS in the design phase.

Electromagnetic interference effects in the bipolar voltage comparator was investigated in this paper. By using of bulk current injection (BCI), the coupling current stimulated by high power electromagnetic pulse was simulated. The experimental results shown that the aberrations such as pulse deriving and pulse width altering will come into being in the output waveforms of LM139 after current injection respectively. Furthermore, the coupling effect of pulse deriving and pulse width broadening were observed simultaneously in the higher level current injections.

Single event transient effect in the linear voltage comparator is investigated in this paper. The circuit level simulation is performed to analyze the output response of LM139 voltage comparators with single event transients (SETs). Simulation results show that input stage and two current sources are the most sensitive parts to the single event transient effects. The output responses were shown as transient pulses with different width. Based on the simulation results, the susceptive parts of a LM139 voltage comparator are acquired. Furthermore, the results above can also be helpful to further harden designs of linear ICs.

When the Minimum channel length shrink to 0.13μιη, As the device geometry size scaling down while the operation voltage of the device decreased, but the electric field increase. The current density is still high in interconnect line, various failure mechanisms still exist in the process generation of copper interconnect/low k dielectric integrated, the reliability is still a very important problem. By using accelerated test, the reliability of the main failure mechanisms have been evaluated, the results showed that the lifetimes of main failure mechanism can achieve the requirements of more than 10 years lifetime. In the same time, NBTI effect will become the main failure mechanism in ultra deep sub-micron CMOS process when Minimum channel length becomes less than 0.13 μιη.

Experimental evidences are presented showing the variety of supply voltage dependence of single event upset (SEU) sensitivity in diverse SRAM devices. Devices under test (DUTs) from Alliance Memory, ISSI and IDT companies with different technologies were irradiated by several kinds of heavy ions at Heavy ion Research Facility in Lanzhou (HIRFL) cyclotrons. For the Alliance 256 kb SRAM device, SEU cross section increases by more than one order of magnitude as supply voltage decreases from 5.0 V to 3.0 V. SEU data of Alliance 64 kb SRAM also exhibits significant supply voltage dependence. The reduction of critical charge is the predominant factor worsening the device performance. While for the Alliance 8 Mb, ISSI 2 Mb and IDT 256 kb SRAM devices, no obvious trend was observed, which is attributed to the negligible net contribution of competing mechanisms. Those results suggest that the worst-case supply voltage for evaluation of SEU sensitivity depends on the test devices.

Along with the infrared technical rapid development, infrared radiation (IR) thermal imaging technology is widely applied in device and circuit reliability research. For device and circuit reliability study, IR thermal imaging technology is best for getting the peak temperature and temperature distribution. With the peak temperature and temperature distribution, the thermal information of the devices were evaluated and optimized to meet the design requirement. Secondly, IR thermal imaging technology is used to position hotspot for failures analysis, example for especially increases in elevated leakage currents. However, IR thermal imaging technology can provide evidence of excessive temperature rise due to power dissipation. It can identify root-cause of failures at temperatures below expectations.

Space traveling wave tube (TWT) is one kind of microwave vacuum tube for communication, which must have high reliability, high power. The life of the space TWT is requested for a long lifetime of 10–15 years. In order to shorten the testing process, accelerated aging tests are performed at higher than normal operating temperature and currents of cathode. But in the process of the actual test, the cathode degradation is very slow, the test time is too long for all samples failing to get the lifetime data. In order to obtain the lifetime of the long life tube in a short time, it is necessary to investigate a new method which can evaluate the long lifetime through short-term working data. This paper introduced how to solve the zero-failure test data with small samples. With no failure data in data processing of life test, parameter degradation extrapolation method is used to obtain the failure life time. All the expected life of the sample was estimated of each test samples by least-square method for linear fitting and the goodness of fit and the significance testing was done.

Inherent reliability of Surface acoustic wave filters plays a key role for its application in the mobile communication systems. Construction analysis is an effective method for evaluating the inherent reliability of electronic components. This work provides a construction analysis process for the surface acoustic wave filters, which includes external encapsulation analysis, internal encapsulation analysis and chip-level analysis. The results show that oxidation occurs on the upper surface of the Al electrodes and leads to the formation of Al2O3. The break in the Al electrode stripe is observed.

This paper proposed a physical model for reverse subthreshold currents in the amorphous silicon thin film transistors. Firstly, an approximation for the band bending in the back interface as a function of gate-source voltage is derived. By considering of deep states, a current model based on electron conduction in the back channel is then developed. Finally, the proposed model was verified using the experimental data.

A prognostic circuit for electromigration failure of integrated circuit was proposed, and it was simulated on the base of the SMIC 0.18 um mixed-signal CMOS process model. The prognostic circuit is composed of stress and detection module, two-stage comparator, offset voltage cancellation module, non-overlapping clock generation module, and output module. When the increase amount of resistance for interconnect line exceeds a preset value due to electromigration, the output of the prognostic circuit designed to fail faster will jump from low voltage to high voltage. It indicates the impending failure of hosted circuit because of that the prognostic circuit experiences the same manufacturing process and operational environment as the hosted circuit. The research results are useful for the prediction of performance degradation and failure of integrated circuit.

Ionization radiation causes ESD protection structure of integrated circuit degradation. A new method using Transmission Line Pulse (TLP) test is introduced in this article; this method gives more detailed information of the ESD protection structure's degradation. Turn-on voltage, hold voltage, turn-on resistance of two type ESD protection structures are measured before and after TID radiation test, results are discussed.

The electromagnetic interference effects in the μA741 operational amplifier circuit were investigated in this paper. Through the using of pulse injection, the output characteristics of μA741 were simulated by considering of EMI effects. Through sensitivity and smoke analysis, the simulation results shown that the differential input stage and the intermediate amplifying stage are the most sensitive and vulnerable function model in the μA741 circuits to EMI effects.

Prognostics and health management has become a preferred approach to achieve warning or respond to impending failure of electronic systems. A prognostic circuit for hot carrier injection (HCI) failure of integrated circuit was proposed in the paper, and it was simulated on the base of the SMIC 0.18 um mixed-signal CMOS process model. The prognostic circuit consists of stress voltage generation module, HCI failure detecting module, two-stage comparator, offset voltage cancellation module, non-overlapping clock generation module, and output module. When the increase amount of threshold voltage for the MOSFET exceeds a preset value due to hot carrier injection, the output of the prognostic circuit designed to fail faster will jump from low voltage to high voltage. It indicates the impending failure of hosted circuit because of that the prognostic circuit experiences the same manufacturing process and operational environment as the hosted circuit. The research results are useful for the prediction of HCI degradation and failure of integrated circuit.

Lifetime is a key parameter for electronic products using, and how to obtain the lifetime by using a short-term aging data has become a challenging issue. In this paper, a new aging data analysis method will be introduced, and three groups of aging data for high power laser diodes will be as a case to expound this method. The aging test time will be greatly decreased by using this method.

We have set up a computer automated controlled diode array reliability experiment which can take up 10 to 20 high power cm-bars. Subsequent 25°C and 50°C lifetime tests were completed. According to the method of least squares, the degradation model of cm-bars is obtained. Using the model and weibull++7 software, the extrapolated lifetime of cmbars at 25°C is 7950 hours (2.86×10 9 shots). We also obtain an acceleration factor 1.88 of resulting in a thermal activation energy of Ea=0.21eV using Arrhenius function. Finally, failure analysis was carried on the gradually degraded devices, the results show that it is the facet degradation which made high power cm-bars degrade during the long time lifetime test.