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A double-sampled delta-sigma (ΔΣ) modulator topology is proposed that can relax the critical timing constraints in the modulator feedback path. The speed requirements of the quantiser and dynamic element matching logic are thus greatly reduced. To verify the effectiveness of the proposed topology, a second-order double-sampled ΔΣ modulator is designed and simulated. [ABSTRACT FROM AUTHOR]

A highly digital technique is proposed for excess loop delay (ELD) compensation in multi-bit continuous-time ▵ ∑modulators. A digitally controlled reference switching matrix is used to replace the powerhungry signal adder and extra DAC driving the quantiser, which are commonly used in ELD compensation. With the proposed technique, the feedback DAC is embedded in the quantiser and implemented by a few switches. Thus, it allows low-voltage and low-power operation. [ABSTRACT FROM AUTHOR]

Two new start-up DAC calibration techniques are proposed for double-sampling ΔΣ modulators. The first one is a modification of the existing calibration technique, while the second technique is proposed specifically for double-sampling ΔΣ modulators. Dynamic element matching is used to eliminate ‘intra-DAC’ mismatches, and digital correction for the remaining ‘inter-DAC’ mismatches. [ABSTRACT FROM AUTHOR]

The low-distortion modulator is an effective ΔΣ ADC architecture for high-linearity and low-dissipation applications. However, it has several practical drawbacks. An improved low-distortion modulator topology that avoids these disadvantages is suggested. [ABSTRACT FROM AUTHOR]

A single-loop delta–sigma modulator with extended dynamic range is proposed. It employs an auxiliary quantiser to process the quantisation error of the main quantiser. This simple addition guarantees improved stability over a wider signal input range and also reduces the sensitivity to the front-end DAC nonlinearity. Simulation results are provided to verify the effectiveness of this structure. [ABSTRACT FROM AUTHOR]

The first-order noise coupling scheme proposed earlier is generalised to the realisation of higher-order enhancement. It is also extended to single-stage ΔΣ loops, and to split structures with self-enhancement. The advantages and limitations of these new ΔΣ architectures are compared with those of conventional single-stage and cascade ΔΣ structures. As demonstrated by an example, they exhibit improved stability and robustness under practical fabrication conditions. [ABSTRACT FROM AUTHOR]